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Verification Futures Conference 2025 UK

The Verification Futures conference has always provided a unique blend of conference presentations, exhibitions, training and industry networking sessions for discussing the challenges faced in hardware and software verification thus providing a unique opportunity for end-users to define their verification challenges and collaborate with the other engineers and vendors to create solutions. In 2025 Verification Futures UK is expanding to include the use of AI/ML in IP/SoC, FPGA and Mixed Signal designs, as well as new tracks for UK Engineering students and UK-based semiconductor start-ups.

Event at a Glance

Tuesday, 01 July 2025 – Full day conference, exhibition and networking event

Reading (UK) & online

FREE to attend conference In-Person or Online

Conference Program

08:30 Exhibition open and student posters available for viewing Slides Videos
09:25 Conference starts
09:30

The four horse riders of the silicon apocalypse

Conference Keynote – Sean Redmond – Silicon Catalyst UK

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10:00

Revolutionizing Verification With GenAI-Powered Automation - A Paradigm Shift Towards Agentic Workflows

Dr Andy Penrose (Cadence)

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10:30 Break - Exhibition open and student posters available for viewing
Main Morning AM
11:00

RISC-V Processor Verification Requires the Complete Toolbox

Simon Davidmann (Synopsys)

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11:30

VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL

Johannes Müller(RPTU Kaiserslautern-Landau)

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VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL
11:50

A novel formal verification solution to Non-convergence

Surinder Sood (ARM)

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12:10

Class-based Design Verification with Python cocotb

Matt Bridle (Doulos)

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Multi Track Session AM
Track 1 :Verification Projects using Open Source/License-Free Tools
11:00

AVL – Bringing Industry Best Practise Testbench Design to Open Source

Andy Bond (Axelera AI)

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11:30

The DV Digest: Improving the Information Space

Brodie Grant(Platform Recruitment)

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11:50

Python-based Verification Vs. SystemVerilog-UVM

Abdelrahman Mohamed Ali(Si-Vision)

12:10

Dynamic CDC Verification: Efficient Approaches for in-house Flows

Christian Tchilikov (semify GmbH)

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Track 2:Training Engineers in work
11.00

Navigating the Verification Maze

Matthew Taylor(Doulos)

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Track 3: AI Design IP
11:00

Securing Chiplet-Based AI Designs: Enabling End-to-End Protection in Modular Architectures

Brice Gaignoux (Secure - IC / Cadence)

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11:30

Testing and verifying the tools of hardware design

John Wickerson(Imperial College London))

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11:50

TechWorks-AI and TAIBOM – Engineering Trustable AI

Gareth Richards(TechWorks-AI)

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12:10

RISC-V: Innovating Within An Established Architecture

James Lewis (RED Semiconductor)

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Track 4: FPGA AM
11:00

Impact of EU CRA and Cyber Regulations on FPGA

Ian Pearson(Microchip Ltd.)

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11:30

Designing reusable, portable and secure IP for FPGA designs

Steinn Gustafsson(Chevin Technology)

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11:50

Unlock Silicon Flexibility: Design for the Future with Programmable Platforms

Owen Bateman (QuickLogic)

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12:10

Bio-inspired CODECs using steganography

Dr Pedro Machado (Nottingham Trent University)

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12:30 – 13:30 Lunch
Main Afternoon PM
13:30

Synergistic stimulus-free verification with next generation static and formal

Yassine Eben Aimine (Siemens EDA)

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14:00

Bringing CI into Formal Verification

Tobias Ludwig (LUBIS EDA)

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14:20

Advanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC

David Kelf(Breker Verification Systems)

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14:40

How Will AI Change Your Verification Future?

Neil Dickins (IC Resources)

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15:30

Multisim: simulate your RTL with real multi-threaded speed

Antoine Madec (Axelera AI)

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15:50

Unify to Verify: A Monorepo Approach for Hardware and Software using Bazel, Cocotb and Verilator

Will Keen(Fractile Ltd)

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16:10

A Novel Security Vulnerability Detection Mechanism Using Information Flow Tracking on a given SOC

Surinder Sood(ARM)

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Multi Track Session PM
Track 1 :Mixed Signal
13:30

A Real Number Model of a Phased Array Antenna

Daniel Cross, Tim Pylant(Cadence)

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14:20

Digital-Mixed-Signal (DMS) Modelling using Signal Flow

Peter Grove(Renesas)

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14:40

EEnet verification of a Multilevel DCDC converter IC

Paul Denny (pSemi)

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15:30

Beyond Boolean: Smart Abstraction Choices in Mixed-Signal Verification

Evgeny Vlasov (Synopsys Inc.)

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16:10

UVM-MS: A Concrete Example using a DAC

Steve Holloway (Renesas)

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Track 2: Design
13:30

The Era of Agentic Engineering – Roadmap to Level 5

Priya Chevuturi (Synopsys)

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14:00

Rethinking chip(let) design for next generation ADAS applications

Martin Zeller(Dreamchip Technologies GmbH)

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14:20

Pre-silicon Identification of Security Vulnerabilities

Doug Carson (Keysight Technologies)

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14:40

Rethinking AI Inference through Differentiable Logic Gate Networks (difflogic)

Georg Meinhardt (DiffLogic Inc. )

Track 3: FPGA PM
13:30

Use of Prototyping and Emulation in the semiconductor industry in 2025

Michael O’Sullivan (Cadence Design Systems)

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14:00

Automating the design of bespoke AI accelerators for FPGAs

Alexander Montgomerie-Corcoran(Heronic Technologies)

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14:20

HDLRegression: A reliable and efficient tool for FPGA regression testing

Marius Elvegård (Inventas)

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14:40

Leveraging FPGA-optimized Equivalence Checking for Security, Safety, and Assurance Standards Compliance

Yassine Eben Aimine (Siemens EDA)

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15:00 Refreshments Break
Track 4: CPU/RISCV Verification
15:30

Automating Cyber-physical Security Verification in the SoC Design Flow

Valentin Peltier (Secure- IC /Cadence)

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15:50

Formal Verification of Security-Properties on RISC-V Processors

Christian Appold (Denso Automotive Deutschland GmbH)

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16:10

𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity

Katharina Ceesay-Seitz (ETH Zurich)

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Track 5: AI in DV
15:30

Efficiency Improvement and Automation in Design Verification using AI

Marmik Soni (Tessolve Semiconductor Pvt Ltd)

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15:50

Case Study on deploying AI in Design Verification for Smarter and Faster Verification of Designs

Arjumand Yaqoob(Qualcomm Incorporated)

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16:10

Validate and Implement a RISC-V core using AI

Vidushi Yaksh, William Ly (University of Southampton)

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Track 6: Breakthrough Technologies
15:30

Splitting the die: a modular approach to chiplet design and verification

Mark Knight (Arm)

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15:50-

TrIM: An Efficient Systolic Array for Convolutional Neural Networks

Dr Cristian Sestito (AI Hub for Productive Research & Innovation in eLectronics (APRIL), The University of Edinburgh, UK)

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16:10

SRAM: Dead or Alive?

Kauser Johar (Chipletti)

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Track 7: FPGA Training
15:30

Improving your VHDL FPGA verification with OSVVM and UVVM

Matt Bridle(Doulos)

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16:30 Drinks and Pizza, student poster competition prize giving, sponsor gift raffle draw
17:00 End of conference

Sponsors

VF2025 was made possible through the generosity of the following sponsors. If you would like to become a VF2025 sponsor please Contact Us.

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