Verification Futures Conference 2025 UK

The four horse riders of the silicon apocalypse

Conference Keynote – Sean Redmond – Silicon Catalyst UK

Revolutionizing Verification With GenAI-Powered Automation - A Paradigm Shift Towards Agentic Workflows

Dr Andy Penrose (Cadence)

RISC-V Processor Verification Requires the Complete Toolbox

Simon Davidmann (Synopsys)

VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL

Johannes Müller(RPTU Kaiserslautern-Landau)

A novel formal verification solution to Non-convergence

Surinder Sood (ARM)

Class-based Design Verification with Python cocotb

Matt Bridle (Doulos)

AVL – Bringing Industry Best Practise Testbench Design to Open Source

Andy Bond (Axelera AI)

The DV Digest: Improving the Information Space

Brodie Grant(Platform Recruitment)

Python-based Verification Vs. SystemVerilog-UVM

Abdelrahman Mohamed Ali(Si-Vision)

Dynamic CDC Verification: Efficient Approaches for in-house Flows

Christian Tchilikov (semify GmbH)

Navigating the Verification Maze

Matthew Taylor(Doulos)

Securing Chiplet-Based AI Designs: Enabling End-to-End Protection in Modular Architectures

Brice Gaignoux (Secure - IC / Cadence)

Testing and verifying the tools of hardware design

John Wickerson(Imperial College London))

TechWorks-AI and TAIBOM – Engineering Trustable AI

Gareth Richards(TechWorks-AI)

RISC-V: Innovating Within An Established Architecture

James Lewis (RED Semiconductor)

Impact of EU CRA and Cyber Regulations on FPGA

Ian Pearson(Microchip Ltd.)

Designing reusable, portable and secure IP for FPGA designs

Steinn Gustafsson(Chevin Technology)

Unlock Silicon Flexibility: Design for the Future with Programmable Platforms

Owen Bateman (QuickLogic)

Bio-inspired CODECs using steganography

Dr Pedro Machado (Nottingham Trent University)

Synergistic stimulus-free verification with next generation static and formal

Yassine Eben Aimine (Siemens EDA)

Bringing CI into Formal Verification

Tobias Ludwig (LUBIS EDA)

Advanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC

David Kelf(Breker Verification Systems)

How Will AI Change Your Verification Future?

Neil Dickins (IC Resources)

Multisim: simulate your RTL with real multi-threaded speed

Antoine Madec (Axelera AI)

Unify to Verify: A Monorepo Approach for Hardware and Software using Bazel, Cocotb and Verilator

Will Keen(Fractile Ltd)

A Novel Security Vulnerability Detection Mechanism Using Information Flow Tracking on a given SOC

Surinder Sood(ARM)

A Real Number Model of a Phased Array Antenna

Daniel Cross, Tim Pylant(Cadence)

Digital-Mixed-Signal (DMS) Modelling using Signal Flow

Peter Grove(Renesas)

EEnet verification of a Multilevel DCDC converter IC

Paul Denny (pSemi)

Beyond Boolean: Smart Abstraction Choices in Mixed-Signal Verification

Evgeny Vlasov (Synopsys Inc.)

UVM-MS: A Concrete Example using a DAC

Steve Holloway (Renesas)

Priyankari Chevuturi (Synopsys) The Era of Agentic Engineering – Roadmap to Level 5

Rethinking chip(let) design for next generation ADAS applications

Martin Zeller(Dreamchip Technologies GmbH)

Pre-silicon Identification of Security Vulnerabilities

Doug Carson (Keysight Technologies)

Rethinking AI Inference through Differentiable Logic Gate Networks (difflogic)

Georg Meinhardt (DiffLogic Inc. )

Use of Prototyping and Emulation in the semiconductor industry in 2025

Michael O’Sullivan (Cadence Design Systems)

Automating the design of bespoke AI accelerators for FPGAs

Alexander Montgomerie-Corcoran(Heronic Technologies)

HDLRegression: A reliable and efficient tool for FPGA regression testing

Marius Elvegård (Inventas)

Leveraging FPGA-optimized Equivalence Checking for Security, Safety, and Assurance Standards Compliance

Yassine Eben Aimine (Siemens EDA)

Automating Cyber-physical Security Verification in the SoC Design Flow

Valentin Peltier (Secure- IC /Cadence)

Formal Verification of Security-Properties on RISC-V Processors

Christian Appold (Denso Automotive Deutschland GmbH)

𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity

Katharina Ceesay-Seitz (ETH Zurich)

Efficiency Improvement and Automation in Design Verification using AI

Marmik Soni (Tessolve Semiconductor Pvt Ltd)

Case Study on deploying AI in Design Verification for Smarter and Faster Verification of Designs

Arjumand Yaqoob(Qualcomm Incorporated)

Validate and Implement a RISC-V core using AI

Vidushi Yaksh, William Ly (University of Southampton)

Splitting the die: a modular approach to chiplet design and verification

Mark Knight (Arm)

TrIM: An Efficient Systolic Array for Convolutional Neural Networks

Dr Cristian Sestito (AI Hub for Productive Research & Innovation in eLectronics (APRIL), The University of Edinburgh, UK)

SRAM: Dead or Alive?

Kauser Johar (Chipletti)

Improving your VHDL FPGA verification with OSVVM and UVVM

Matt Bridle(Doulos)