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Center of Excellence

Convergence of Experts – Driving Semiconductor Innovation

Tessolve is the market leader in providing engineering solutions for silicon and systems development. Tessolve has taken a further step to establish a Center of Excellence (CoE) in the various areas of Test Engineering, VLSI Analog, VLSI Digital, Embedded Systems, Special Projects, and PCB for large-scale adoption of newer technologies and innovations. We have been thinking ahead to establish and empower CoE, invest in future competencies to leapfrog the competition, identify solutions for complex business problems, and develop new areas for growth. This differentiates Tessolve from other companies that are focused on narrow offerings.

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end-to-end

Leading end-to-end solutions provider & technology partner for semiconductor companies. Thinking ahead to establish and empower the Center of Excellence (CoE).

growth

Invest in future competencies to leapfrog the competition, identify solutions for complex business problems, and develop new areas for growth.

Design-Engineering-icn

Established CoE in VLSI, Test Engineering, Embedded Systems, PCB, and special projects.

Our Center Of Excellence

Chip 1

RISC-V SoC

RISC-V is an open-source ISA with unparalleled customization, scalability, and flexibility. Our TSoC1 solution leverages these features for diverse applications, including Automotive, IoT, Mobile, Cloud, Data Center and Embedded Systems.

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TSoC1 has necessary peripherals such as USB, DDR3, Ethernet, and more, providing a fast and cost-effective market entry. TSoC1 is verified with C-tests and UVM, and its design and test environment can be easily adapted. With a projected 25% CAGR growth and a market size of 500 million USD, RISC-V offers endless opportunities.

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Chip 8

PSS

SoC verification requires simulation, emulation, and FPGA prototyping to verify complex designs from the block level to subsystems and full SoC.

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Each platform has its own language for specifying tests, which are often composed by different teams as well, and too much time and effort are spent recreating the same test information throughout a project. The Portable Stimulus Standard (PSS) was developed to solve the portability challenge. PSS allows tools, to automate test generation that is portable across vertical reuse(IP, Block, subsystem, and SoC level) and horizontal reuse(Simulation, emulation, FPGA prototyping )and maximize test coverage. Tessolve has already developed significant expertise in creating a PSS model and can support companies in their SoC verification.

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Chip 4

Chiplet

The market is moving away from monolithic SoC towards SiP (System in Package)

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where we build systems from discrete "chiplets" and connect them inside a package This introduces challenges in the way we test design and test chiplets and the SiP to ensure we can get the required final yield numbers within acceptable test times. Tessolve has already developed significant expertise in this area and we can support companies on their transition from SoC to chiplets and SiP.

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Test

SLT

It is becoming increasingly difficult to meet test coverage targets in larger, more complex chips and this can create yield issues.

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SLT (System Level Test) adds additional tests by putting the final packaged device into an environment that mimics its target system environment and can provide additional test coverage. This requires additional hardware and embedded software, as well as a good understanding of the DfT and ATE environments to align traditional and SLT strategically. Tessolve is already providing services to enable our clients to move to SLT. We are also working with major ATE Test Equipment manufacturers to ensure practical SLT solutions. Finally, we are developing an IEE 1149.10-based solution to enable faster scan test within an SLT environment.

Know More SLT

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Iso

ISO26262

Automotive Manufacturers are making strides towards fully autonomous vehicles where Functional safety is paramount for the safety of passengers and pedestrians.

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There is a demand for ensuring safety standards throughout the life cycle of vehicle development. ISO 26262 is an international standard for functional safety in the automotive industry. The ISO 26262 standard ensures that sufficient levels of safety are being met and maintained throughout the vehicle lifecycle. One of the prerequisites for entering the automotive sector is to get ISO26262 certification for all BUs at Tessolve which gives confidence to the customer that we are complying with the automotive standards and avoiding costly recalls & reputational damage due to safety hazards. Tessolve is presently working on training the Engineers on ISO26262 standards & getting process certification to meet customer requirements.

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Chip 3

AI & Computer Vision

AI at the service of human: EdgeAI and computer Vision solutions from Tessolve enable to solve of customer problems when the standard algorithm does not:

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Digitization of analog metering using AI Optical Character Recognition, Early Failure detection of a machine before the system break using Predictive Maintenance AI and many more. Those solutions are cost and power-optimized and respect privacy. The proposed approach is in two steps: Step1 : Check with a PoC that AI can solve the customer issue: A feasibility study to validate AI algorithm meet expectation criteria in term of reliability and predictability. Step2 : Complete development to integrate AI into the system.

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Microscope

PSV Lab

PSV Lab Targets various SOC manufacturers to provide an end-to-end solution. Power Measurement – helps to measure the power consumption of various system components of Embedded devices in different user scenarios.

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Power requirements are an important parameter. As embedded systems become smaller and faster. To achieve prolonged battery life and improved reliability. Performance - is a testing measure that evaluates the speed, responsiveness, and stability of a computer using workloads. Performance metrics commonly include - Throughput, Memory, Response Time, Bandwidth & CPU interrupts per second.

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Chip 1

Embedded Systems CoE

Embedded Systems Group displayed the latest SoC-based SoMs from NXP (S32G and IMX8M PLUS) and TI (AM62X- SITARA).

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A live demo of Flutter-based applications on AM62X was shown for Internet Radio, an automotive cluster, and an animation screen. TERA unit with industrialized design for automotive gateway has been showcased. Some of these demos were also showcased in Embedded World, NXP Tech Days, and CES. The S32G and AM62X SoM are SMARC 2.1 standard ones and have a Nano ITX size application board designed by Tessolve. The IMX8MPLUS SoM is the first OSM standard SoM module developed by Tessolve Embedded System Group. These SoMs have high-performance multi-core CPUs and dedicated MCUs with a rich set of peripheral interphases including High-speed memory, GBE, Multiple CAN, LIN, SERDES, and Multimedia interfaces. The SoMs are suitable for Automotive gateway and Industrial IoT applications and can be easily customized for the optimum requirement of customer needs. The TERA box is field tested and qualified. All the SoMs are supported with the required firmware for the peripheral devices.

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Chip 8

Embedded Services CoE

ADAS Traffic Sign Detection: Most Accidents [90%] are due to human errors.

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Traffic sign detection is one application that alerts the driver to take action. We implemented the application and tested it with Matlab in lab.

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Chip 6

Embedded Services EV

Electric Vehicle application development for Battery Management systems.

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We want to develop algorithms for the State of Charge, State of Health, and Active and Passive cell balancing algorithms. we had made requirements and designs for SOC & SOH.

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Chip 1

SI/PI ( PCB & Package)

Signal data rate and power distribution noise pose challenges in the development of interconnect designs.

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designing IC Packages and PCBs for proper functionality is important and SI/PI simulations play an important role in design sign-off. At Tessolve we have integrated SI/PI process with the design flow to ensure optimized design output, equipped with infrastructure and software to address technology demand.

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Design Engineering Icn 03

PCB Automation

Automate DUT to Tester channel assignment in an ATE Test board. DUT pins need to be wired to Tester channel pins for Functional and Continuity tests.

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An AI-based tool is under development to automate this assignment, using matching algorithms, following all constraints, and with a target to have routing done with minimal PCB layers and routing length. The tool is also expected to do auto-routing as well which will significantly reduce PCB design cycle time. The target completion date for the tool is May '23 and when successfully deployed the expected reduction in an ATE board cycle time is min 10%.

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Tool

FEAST

FEAST is a tool that automates the feasibility study of a DUT on an ATE platform.

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Features like capturing DUT Pin List, Pin Specifications, and assigning Tester Resource are built into the tool. Every stage of the feasibility process is peer reviewed and approved by the TEST manager at appropriate stages. FEAST also has the capability to estimate Test Time, Coding, Debug, and correlation time for a given test list in a much quicker way. FEAST not only improves the efficiency of doing a feasibility study but also to do it more accurate.

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Test

Customized RF Test System Development To Test RF Switches

Tessolve built a low-cost custom RF Tester to test mobile phone RF front-end switches used to select between the different antenna and RF signal paths

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The tester which addresses the challenge of cost efficiency by maintaining scalability and increasing ATE longevity. The RF front-end switch is a growing market predominantly in the mobile phone sector and there is a high demand in the industry for reduced test costs for such switches. The tester built by Tessolve was able to provide >50% lower test times as compared to legacy ATE via a quad-site test solution. The tester is capable to test upto 6GHz RF front-end switches and is scalable to octal site testing.

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Sensor

Image Sensor Custom Test Solution Development

Tessolve built a Low-cost tester capable of testing image sensors, which addresses the challenge of cost efficiency by maintaining scalability and increasing ATE longevity.

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The image sensor is a growing market predominantly in the mobile phone sector and there is a high demand in the industry for reduced test costs for such sensors. The tester built by Tessolve was able to provide 30% lower test times as compared to legacy ATE. The tester is capable to test 256 pairs of LVDS lines up to 800Mbps speed. Add-on features like structural patterns up to 128 M scan depth are also integrated. We have developed an Image processing library using C# that is capable to detect any fault in the image captured.

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Chip 3

HSIO Capability Demo

Tessolve has now the cutting edge Latest HSIO Bench Characterization equipment which could test up to PCIe Gen 6(112 GBPS PAM4)

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Including the capability to Characterize DDR5, and USB4 and could do advanced measurements like ISI/Crosstalk/Jitter Analysis along with de-embedding and equalization techniques. We have the software licenses to do TX/RX Compliance parameters up to DDR5/PCie Gen6/USB 4 etc.

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Partner

FA & Reliability

Currently, the HTOL oven in Tessolve is utilized for Pattern bring-up, BIB board bring, and actual qual stress execution.

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Pattern bring-up and BIB board bring-up activity will take 2 to 6 weeks. During this time HTOL oven is ideal and not effectively utilized. To overcome this we have Designed and developed an HTOL Pre station which is stand-alone and can be used for bring-up activities during this time HTOL oven can be used for other project execution. By implementing this Pre station, HTOL equipment can be effectively utilized. Requesting the sales team to use this info during customer interaction.

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Chip 5

Complex ATE Load Board Designs/Manufacturing For Multiple Testers

The placing of ~6200 relays in the available area of ETS800 hardware and the Effective utilization of 192-Control bits to control ~6200 relays individually was challenging.

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With the Innovative way of component placement and also customized CBIT circuitry (NC/NO technique) we managed to achieve a 16-site ETS800 solution which helped to achieve ~98% parallel test efficiency resulting in Test cost reduction.

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Test Bench Activities Icn 03

ETS88 Test Infrastructure Setup

Tessolve is capable of handling the conversion of any old legacy tester to a

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state-of-the-art road map tester and fully owns the responsibility of setting up the HW and SW infrastructure as well as a standard process to qualify test solutions for production release and finally enabling the customer to confidently own the responsibility to continue developing test solutions on the new platform independently.

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Serach

Cell Aware Scan Test

Conventional fault modeling tests such as SAF & TDF are not sufficient to achieve low DPPM for complex designs at lower technology nodes,

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especially applications such as Automobile and Medical SoCs. We are skilled with Advanced Fault modeling tests such as Cell Aware & Small delay defect tests (CAT & SDD) that would provide higher defect coverage and lower DPPM at the cost of increased VM & TT. CAT targets the faults corresponding to the internal cells where as SDD covers paths with minimum time slack. Tessolve has the capability to build Test programs including the CAT & SDD test cases and correlate the DPPM results with and without Advanced fault modeling tests.

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Test 3

DDR/HSIO Test Capabilities & Multi-channel Test Challenges

Tessolve is specialized in validating DDR all the way from Gen1 to Gen5. The latest technology includes LPDDR5 tested up to the highest frequency - 4.2Ghz for mobile applications & up to 3.2Ghz for AR/VR/Mobile/Automotive/Server based products.

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Other high-speed interfaces like USB & PCIe Gen4 are tested up to 20Gbps & 16Gbps data transfer speeds respectively. One of the recent problem-solving abilities is manifested through a unique IO calibration method where cost & efforts of Design change are saved ensuring no delays in time to market of a product & no impact on real applications.

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Download The Resource

Chiplet White Paper

3 Year Plan

System Level Test (SLT)

Know More About How Tessolve Can Help

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