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Takes Wings At Tessolve

Careers

Why join Tessolve?

At Tessolve, we help individuals realize their full potential, fostering excellence with our wholesome working environment. To our employees, we bring exposure to latest technology, and an opportunity to explore the application of silicon engineering across a wide breadth of industries. It means, you have the chance to work with globally diverse customers on cutting edge engineering projects while growing with a top tier company that is a pioneer in hardware testing.

You are welcome to – Join the Tessolve family.

Join Us

If you are –

Work Benefits

Perks of being at Tessolve

  • Compressed work week
  • Transport assistance
  • Provision for lunch, coffee and tea on-site
  • Enrollment to Employee Provident Fund scheme
  • Medical insurance for employees and dependents
  • Gratuity scheme for employees working 5 years and beyond
  • Attractive monthly Earned Leave credits and accrual limits
  • Flexible work options for certain cases and situations
  • On-site gym, TT table, and so much more

The Tessolve Worklife

Not work but growth as it should be

Open Positions

We are ready for you. Are you too?

QMS Executive

Experience: 2 to 3 years

Education: BE – ECE / EEE

No Of Position: 1

Location: Bangalore

Job Description:

  • Experienced with active role towards deployment and Sustenance of ISO systems.
  • Preparation and maintaining schedule for Audits.
  • Guidance to Internal Auditors.
  • Preparation of procedures, forms, Work instructions, SOPs, etc,.
  • Amendments as requested by users for existing procedures upgrades.
  • Details collection for reports, Audit consolidation reports and followups.
  • Communication with different groups for strengthening the existing systems.
Apply Now

Test Engineer - Post Silicon Validation (Dallas)

Experience: 2 to 5 years

Education: BE / ME / MS Electronics & Communication

No Of Position: 1

Location: Dallas – USA

Job Description:

  • Leverage various post-silicon lab and ATE platforms to characterize and ensure a semiconductor product meets all specifications and works robustly in the customer’s end equipment.
  • Timely development of accurate and innovative bench validation solutions for logic and translation devices.
  • Drive a project from beginning to end with complete ownership and minimal supervision.
  • Work with systems engineers to define the system level validation tests for customer use conditions, voltage and temperature extremes, and stress to failure tests in the Validation & Verification Compliance Matrix (VVCM).
  • Develop a detailed characterization plan to test device specification and define the instrument resources required to perform each test.
  • Using a collected characterization data set, a validation owner makes an independent assessment of all device functionality and datasheet information, ensures correlation with Design/Verification, and verifies that the device meets the customer’s needs.

Responsibilities:

  • Develop test fixtures, PCB boards, and work with IC socket vendors.
  • Document issues and work with various functional teams to identify the root cause and the proposed fix.
  • Driving key validation reviews (E.g. Test Plan, PCB Schematic and Layout, Software, Silicon Evaluation).
  • Analyzing statistical data and translate into operational limits to guarantee device performance.
  • Correlate bench results with Verification test benches and production ATE equipment.
  • Proactive communication skills to effectively work with core Design / Product / Test / QA teams and external customers.
  • Proven knowledge of analog circuits and automated test Proficiency with bench test equipment (i.e. PXI instrumentation, oscilloscopes, digital pattern generators).
  • Ability to work in a hands on environment testing devices in the lab Basic knowledge of PCB schematic capture, layout and fabrication process.
  • Analyze statistical data and understand basic statistical concepts such as mean, standard deviation, and variance.
  • Experience with LabVIEW, TestStand, Spotfire, Python, and/or other programming skills, Management / Organizational Skills.
  • Ability to collaborate with internal cross functional teams, Strong project management, multi-tasking, problem solving and communication skills are important in this role.
  • Must possess the ability to effectively negotiate with test equipment, PCB turnkey, and IC socket vendors Projects and Deliverables.
  • Develop and implement continuous improvement initiatives to reduce new product cycle times and release many product spins.
Apply Now

Physical Design _Full Chip Design (Automotive Domain Expert)

Experience: 7 to 18 years

Education: Any Engineering Degree or equivalent practical experience.

No Of Position: 1

Location: Bangalore

Job Description:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs ( Preferably below 28 Nm like 16/14/12/7 nm).
  • Experienced in leading SOC timing closure and physical design tasks with deep technical knowledge in all.
  • Experienced in Full Chip PNR & Partitioning / Bump Placement.
  • stages of the design (floor planning, placement, clock-tree-syntheses CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
  • Experience in Low power and high performance design.
  • Experience in designing for Automotive industry.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements.
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Expert in tools Cadence Encounter/ Magma Talus/Synopsys ICC / Cadence Innovus.

Experience:

  • Full Chip SOC.
Apply Now

ATE Test Engineer – Advantest 93K and SmartRDI Programming

Experience: 3+ years

Education: BE / ME in Electronics and Communication

Location: Dallas – USA

Roles and Responsibilities:

  • Develop test programs (Java/C++) for digital devices on the 93k platform.
  • Test Program development, debug and resolving SmarTest SW issues.
  • Write scripts (perl/python) and tools to assist customers in improving their process quality and time to market.
  • Must have Semiconductor testing knowledge.
  • Should have very good experience in test development and debug.
  • Digital and PMIC experience with Smart RDI programming – a major plus.
  • Knowledge on Programming concepts and C/C++, Java language – preferred.
  • Strong communication & statistical analysis skills.

Skills Preferred:

  • Bachelor’s or Masters in Electronics or computer science.
  • Min 3 Years of Experience in Advantest 93K tester (should be familiar with SMT 7 & 8).
  • SmarTest 7 or 8 hands-on experience.
  • Proficient in 93k digital testing and vector debugging (shmoo, pin margin, timing debug).
  • Multiple years of experience on the 93k platform.
  • Smart RDI Programming.
  • Strong 93k DC testing experience.

Good to have skills:

Apply Now

Software Engineer

Experience: 1 + years

Education: BE (CSE / IT) / MCA

Notice Period: 1 Month

Location: Vizag

Skills & Experience:

  • 1+ years of hands-on experience on ‘Digia Qt’.
  • 1+ years of hands-on experience on ‘C++’ or ‘C#’.
  • 3+ years of ‘Digia Qt‘ expertise in designing and developing solutions.
  • Ability to design and develop independently follow development processes, reviews and integration to handle releases.
  • Strong ability to understand existing code and create quality code from design models/documents.
  • Good understanding of object oriented design and knowledge of product life cycles.
  • Experience with any ATE test systems highly desirable.

Responsibilities:

  • As a Senior Software Engineer – you will contribute to analysis, design & development of features, creation of work plans.
  • You must be able to understand requirements, existing features, design and architect solutions.
  • You will have opportunity to learn and implement both existing and new technologies, especially Digia Qt and C++/C# on Windows platform.

Additional Skills:

  • Programming knowledge on VBA, Python, MATLAB & Perl.
  • ATE – Pattern Conversion tool development experience.
  • Digital logic basics.

Good to have skills:

Apply Now

Physical Design

Experience: 4 to 8 Years

Education: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

No. Of Positions: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Job Description:

  • Ability to handle the complete physical design and analysis of multiple designs independently.
  • Good understanding of the static timing analysis and experience of closing timing requirements on multiple designs.
  • Experience of closing power analysis (IR/EM), equivalency checks as well as low power checks.
  • Ability to run the physical verification as well as fix all the violations independently.
  • Exposure to the challenges in the physical design of chips targeted to 28nm/16nm / 7nm technology.
  • Experience in writing scripts using standard scripting languages (TCL/Perl).
  • Good communication skills.
  • 4 years of experience in physical design.
  • The job will involve working on multiple block level designs to close all the implementation, timing, power, and physical verification-related issues.
  • The candidate is also expected to contribute to the chip level analysis runs and solve some of the complex issues in the design.
Apply Now

Physical Design Expert - SOC/IP/Sub-System Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 15 years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs (28/14/7nm) and associated issues (manufacturability, power, signal integrity, scaling).
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all.
  • Stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
  • Experience in Low power and high performance design.
  • Experience in designing for automotive industry.
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements.
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
  • Good understanding of mixed-signal building blocks.
  • Understanding of power management and its implication on physical design.
  • Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS.

Experience:

  • SOC/IP/Sub-System Design.
Apply Now

DFT Engineer

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • The person hired in to this role will be contributing to DFT insertion and validation effort of complex DSP core.
  • In depth knowledge of DFT concepts.
  • In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
  • In depth knowledge and hands on experience in MBIST insertion and Memory test validation.
  • Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
Apply Now

DFX / DFT Architect

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Preference: Candidate from semiconductor back ground

Requirements:

  • Strong knowledge of DFT architectures & methodologies. This includes Scan, BScan, IO DFx, analog DFT, JTAG, Boundary scan, etc with minimum experience of 4+ years.
  • Proven knowledge of Verilog , RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology (Synopsis VCS* and Verdi, Lintra, Spyglass, Tessent ATPG tools, Synopsys ATPG tools, etc).
  • Strong Si debug skills, ATE requirements and understanding of volume test requirements. Strong Communications skills and the ability to effectively work with cross functional teams across geographies.
Apply Now

ASIC Synthesis

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 6+

Location: Bangalore

Requirements:

  • Good understanding of VHDL or System Verilog.
  • Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation.
  • Development of signoff quality SDC constraints and the development of power intent constraints.
  • May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.
  • Hands-on with Synopsys DC/DCT/DCG/DE-Explorer.
  • Hands-on with Synopsys Prime Time including SDC constraint development for complex blocks with many clock domains.
  • Hands-on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
  • Experience with either RTL development or Physical Design is also a plus.
Apply Now

Synthesis/STA

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 12 years

No of Position: 4 (Lead / Experts)

Location: Bangalore

Requirements:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues.
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure with deep technical knowledge in all.
  • Stages of the design – functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Experience in Low power and high performance design.
  • Experience in designing for automotive industry.
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements.
  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
  • Good understanding of mixed-signal building blocks.
  • Understanding of power management and its implication on synthesis/STA.
  • Expert in tools – any vendor.
Apply Now

RTL Design / Integrations

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 5+

Location: Bangalore

Requirements:

  • Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores.
  • Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation.
  • Demonstrated success in completing projects using high-speed logic design.
  • Experience with synthesis, Lint, CDC, and LEC.
  • Knowledge of protocols such as PCI-Express, RapidIO, NVM Express and LP DDR2/LP DDR3.
  • Candidate must have excellent Verilog and System Verilog concepts, and experience in verification of complex RTL designs and validating them on the boards is an added advantage.
  • Working knowledge of UNIX environment and scripting languages (PERL, Python/TCL etc) desired.
  • Strong analytical skills with attention to detail.
  • Excellent written & verbal communications skills.
  • Very good leadership skills.
Apply Now

Lint / CDC / Synthesis

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4+

Location: Bangalore

Requirements:

  • Synthesis Constraints development, LINT checks, CDC checks.
  • Working / leading full-chip STA closure, defining mode requirements & corners for timing closure.
  • Formal Verification-Synopsys Formality/ Cadence.
  • CTS & ECO cycle.
Apply Now

FPGA Emulation

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 4+

Location: Bangalore

Requirements:

  • Creates Emulation models from RTL design using Emulation tools.
  • Strong expertise into Emulation with Palladium, Veloce platforms at least one of them.
  • Should have good knowledge in implementing Bigger designs in multiple FPGA’s/HAPS platforms.
  • Familiarity with FPGA synthesis.
  • Working knowledge XILINX Virtex FPGA architecture and experience with ISE tool flow.
  • Good Knowledge of protocols: AXI/AHB, bridges, memory controllers such as DDR/Nand, and peripherals such as USB, PCIe, USB, &, Memory.
  • Good programming skills i.e. Verilog, VHDL, SV, C/C++ is a must.
  • Knowledge of Virtex or Kintex UltraScale is a definite plus.
  • Good written and oral communications skills required.

Experience:

  • Latest FPGAs Virtex-7 or Kintex-7 and above.
Apply Now

SOC/ IP Verification

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 10 (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • The ideal candidate should be a hands-on expert in verification using System Verilog and have hands-on expertise in utilizing modern verification methodologies like VMM/UVM/OVM, to be part of the verification team of core IPs and complex subsystems with 4+ yrs. of experience.
  • Experience with verification methodologies such as UVM/VMM/OVM is required, and a strong understanding of UVM is preferred. Candidates are expected to have designed and developed UVM, SVTB and have previously composed functional coverage assertions, preferably using System Verilog.
  • Proficient on protocols – PCI-Express, RapidIO, NVM Express, LP DDR2/LP DDR3, AXI, AHB, USB, HDMI, MIPI, & ethernet.
Apply Now

Memory Circuit Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4

Location: Bangalore

Requirements:

  • Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF Technologies.
  • Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
  • Development of critical path and characterization flow to perform detailed margin and characterization simulations.
  • Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off.
  • Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
  • Logic simulations and detailed timing analysis of key paths in high speed memory design.
Apply Now

IO Layout

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 3 to 8 years

No of Position: 2

Location: Bangalore

Requirements:

  • Good Knowledge about IO Layout, should have work experience on 28nm (Below 28nm is highly preferable).
  • Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS.
  • Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation in Layout Design.
  • Sound knowledge of IO blocks like Design of the Transmitter /Receiver Blocks, Level Shifters.
  • Exposure to DDR IOs, XTAL IOs an added advantage.
  • Very Good CMOS fundamental.
  • Good Communication Skill.
  • Skill/Perl programming knowledge is an added advantage.
Apply Now

Analog Circuit Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 6

Location: Bangalore

Requirements:

  • Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
  • Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
  • Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
  • High Speed Latch,High Speed Rx Front End.
  • Must understand Solid state physics, Short Channel Effects, Lower Process node trade-offs,K-MAP, Boolean Algebra.
  • Must understand Matching Device Concepts,ESDS,Latup, Antenna effect, Modeling spice/AMS.

Good to have:

  • Must have worked on atleast one of the Block Design with Full Ownership.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • Power Management Blocks such as LDO, Buck Boost,Switching Regulator for more than 1A regulated Output Current.
Apply Now

Analog Layout Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 6

Location: Bangalore

Requirements:

  • Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
  • Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
  • Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
  • High Speed Latch,High Speed Rx Front End.
  • Must understand Fabrication steps, short channel effects, EM, IR Drop, RV Violations.
  • Must understand Matching Device Concepts, ESDS, Latup, Antenna effect, Common Centroid, Interdigitized Matching Tradeoffs.

Good to have:

  • Must have worked on atleast one of the Layout Block with Full Ownership.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • Power Management Layout Blocks such as LDO, Buck Boost, Switching Regulator for more than 1A regulated Output Current.
Apply Now

AMS Verification

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4

Location: Bangalore

Requirements:

  • Experience in Analog and Mixed Signal (AMS) verification.
  • Hands-on experience in C/C++ based verification and SV/UVM based verification.
  • Strong fundamental knowledge of analog circuits behavior.
  • Ability to write models using Verilog/Verilog-AMS.
  • Understanding complete verification flow.
  • Experience in SV/PSL assertion methodology.
  • Hands-on experience on Cadence and other tool flows.
  • Gate level simulation experience is an advantage.
  • Good Communication skills.
  • Strong problem solving and analytical skills.
Apply Now

Manager / Lead Test Engineer

Qualification: BE/ME in ECE/EEE

Experience: 6 to 10 Years

No of Position: 1

Location: Bangalore

Requirements:

  • Candidate should have minimum 6 to 10 years experience in semi-conductor testing
  • Responsible for working with different teams for understanding the device datasheet and come up with a detailed Test procedure/plan to test the chip in ATE environment
  • Need to interact with the PCB design team for developing the necessary hardware – Test load board, bench board and probe cards
  • Should be responsible for developing the complete ATE test program to validate the chip
  • Should invlove in developing the test methodologies as required

Responsibilities:

  • Work with design/DFT team to develop the detailed test procedure from device data sheet
  • Design and develop the required test hardware- Load board, bench board, Qualification board and probe card
  • Develop the ATE test program for device debug
  • First silicon verification and device bring up using ATE tools and bench equipment
  • Device characterization across temperature, voltage and process corners and validate the chip against the specification
  • Responsible for releasing  the Final production quality test program to the customer (both wafer final test program)
  • Interactions with the Design/DFT team through out the project execution
  • Interact with the customer on a daily basis and provide status update through e-mails and conference calls.
  • Experience in test program release procedure at production test house
  • Responsible from the beginning to the Final test/Wafer Test program release at customer site
Apply Now

Layout Design Engineer

Qualification: BE/ME in ECE/EEE

Experience: 3+ Years

Requirements:

  • Substrate layout design, cadence tools
  • PCB routing,Library creation, RDL routing, simulations
  • Substrate material knowledge is added advantage

Responsibilities:

Apply Now

IP/SoC Logic Design Engineer

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 – 15 years

No of Position: 3

NOTE: This is for ONSITE to US and Valid H1B VISA is Mandatory

Job Description:

  • Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs
  • Participates in the development of Architecture and Microarchitecture specifications for the Logic components
  • Evaluates new feature requests, Designs and develops IP features
  • Provides IP integration support to SoC customers and represents RTL team
  • Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design

Responsibilities:

Apply Now