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Takes Wings At Tessolve

Careers

Why join Tessolve?

At Tessolve, we help individuals realize their full potential, fostering excellence with our wholesome working environment. To our employees, we bring exposure to latest technology, and an opportunity to explore the application of silicon engineering across a wide breadth of industries. It means, you have the chance to work with globally diverse customers on cutting edge engineering projects while growing with a top tier company that is a pioneer in hardware testing.

You are welcome to – Join the Tessolve family.

Join Us

If you are –

Work Benefits

Perks of being at Tessolve

  • Compressed work week
  • Transport assistance
  • Provision for lunch, coffee and tea on-site
  • Enrollment to Employee Provident Fund scheme
  • Medical insurance for employees and dependents
  • Gratuity scheme for employees working 5 years and beyond
  • Attractive monthly Earned Leave credits and accrual limits
  • Flexible work options for certain cases and situations
  • On-site gym, TT table, and so much more

The Tessolve Worklife

Not work but growth as it should be

Open Positions

We are ready for you. Are you too?

Connectivity (Bluetooth & WIFI)

Experience : 3 to 6 years

Domain : Automotive

Education : BE / B.Tech – CS / Electronics

Location : Chennai

Key Skills :

  • IVI Testing (Must).
  • Defect Triaging (Must).
  • Bluetooth and Wi Fi (Must).
  • Wifi/Bluetooth/USB/Display/Touch – Any one is fine.
  • C++/Java/Android framework is preferred.
  • Unit testing and Integration testing of Android Automotive applications.
  • Git, Gitlab, gerrit and RTC (Nice to have).

Technical Skills:

  • 3 to 8 years of experience in automotive embedded software development (Must).
  • IVI in Android experience (Must)..
  • Design and implementation of new software architectures based on Linux and Android for high-performance computing platforms for embedded automotive applications.
  • Experience in any generic drivers (i2c/spi/usb/i2s/).
  • Good ‘C’ programming skills and better to have object-oriented programming skills, preferably in C++.
  • Experience in development and/or integration of Linux based for automotive embedded applications.
  • Experience in any one of drivers are prefer (Wifi/Bluetooth/USB/Display/Touch).
  • Familiarity with tools like JIRA, GitHub, Jenkins etc.
  • Elaboration of technical documentation and reports.

Primary Responsibilities:

  • Infotainment Bluetooth/Telephony feature Validation.
  • Testing WiFi stack in Infotainment.

Detailed Description:

  • Solid expertise in Automotive IVI Testing and Defect Triaging.
  • Experience in Bluetooth and Wi Fi domains is mandatory.
  • Experience in C++/Java/Android framework is preferred.
  • Expertise in Unit testing and Integration testing of Android Automotive applications.
  • Hands on experience with SCM tools and services such as Git, Gitlab, gerrit and RTC.
Apply Now

OSB BSP

Location : Bangalore / Chennai

Position(s) : 9

Minimum Qualifications:

  • 3 to 8 (Senior S/W Engineer in Automotive Embedded S/W development.
  • IVI in Android experience (Must).
  • i2c/spi/usb/i2s  Any one is fine.
  • Wifi/Bluetooth/USB/Display/Touch – Any one is fine.
  • C & C++.
  • JIRA, GitHub, Jenkins – Nice to have.
  • Determines operational feasibility by evaluating analysis, problem definition, requirements, solution development, and proposed solutions.
  • Handle dependencies and interfaces to other functional areas and subprojects proactively.
  • Particpate in sprint grooming meeting along with other component leads to understand the feature delivery, dependencies, impediments.
  • Ensure software release on time.
  • Support Technical delivery manager and quality team during internal and external audit for Non-compliance.
  • Report status, issues and progress of the SW development to the SW project lead.

Technical Skills:

  • 3 to 8 years of experience in automotive embedded software development (Must).
  • IVI in Android experience (Must)..
  • Design and implementation of new software architectures based on Linux and Android for high-performance computing platforms for embedded automotive applications.
  • Experience in any generic drivers (i2c/spi/usb/i2s/).
  • Good ‘C’ programming skills and better to have object-oriented programming skills, preferably in C++.
  • Experience in development and/or integration of Linux based for automotive embedded applications.
  • Experience in any one of drivers are prefer (Wifi/Bluetooth/USB/Display/Touch).
  • Familiarity with tools like JIRA, GitHub, Jenkins etc.
  • Elaboration of technical documentation and reports.
Apply Now

Media

Location : Bangalore / Chennai

Position(s) : 1

Minimum Qualifications:

  • 4 to 5 years of Experience.
  • Multimedia (Must).
  • POSIX internals (Must).
  • Audio/Video frameworks (knowledge is fine) .
  • Java, JNI, C, C++ (Java & C++ is fine).
  • Multi-threading & Middleware.

Key Job Responsibilities:

  • Understand different system requirements and SW requirements.
  • Contribute to design and development.
  • Develop the SW requirements as per given design.
  • Understand integration requirement with Access delivery.
  • Implement Widevine DRM.
  • Understand work with Media/MBS modules.

Key Performance Indicators:

  • 4 to 5 years’ experience in embedded systems development.
  • Multimedia experience preferred.
  • Android knowledge is a plus.
  • Strong hands on expertise in Multi-threading programming and middleware solution development, IPC o POSIX System concepts and POSIX internals ((POSIX expertise) o Java, JNI, C, C++ programming skills o Knowledge of any of AAP, CP, CL is a plus.
  • Strong hands on expertise in Good Fundamentals of IPC and OS concepts. o knowledge of audio/video frameworks. o Troubleshooting issues on run-time environment.
  • Understanding of decoding, audio and video rendering.
  • Strong problem-solving skills.
  • Strong communication and inter-personal skills.
Apply Now

Android Framework

Location : Bangalore / Chennai

Positions : 5

Minimum Qualifications:

  • B.S. or M.S. in Computer Science or equivalent software development experience.
  • 4+ years of experience in coding in C/C++ and/or Java.
  • 3+ years experience building Android services and/or applications using Android SDK.

Preferred Qualifications:

  • Experience working with Android frameworks, AOSP Graphics (Telephony, Camera2, Multimedia, OpenGL, Connectivity, etc.).
  • Understanding of Android SDK, JNI and Binder IPC mechanisms.
  • Good understanding of mobile performance, latency, and security issues.
  • Experience optimizing for multiple device screen sizes and Android versions.
  • Experience shipping high quality consumer applications and products.
Apply Now

Firmware Developer

Location : Bangalore

Experience: 3 to 10 Years

Requirements & Skillset: All engineers should be well versed with Linux and QnX device driver and middleware frameworks for the following modules:

  • Multimedia: MIPI-CSI, Image capture and processing IP, Scalars, H/W Video codec acceleration (typically MFC for exynos), ALSA and other audio driver layers.
  • System Interface: System bring-up, USB, Ethernet, UFS, PCIe.
  • Graphics: GPU, Display, HDMI.

Job Description

  • All engineers will be required to develop device drivers as listed above, compatible with QnX RTOS on Samsung’s Exynos Auto V9 SoC.
  • Each device driver owner should be able to understand the Linux framework for their respective IPs and migrate the drivers to QnX.
  • Each device driver owner should be able to migrate or port QnX drivers from older version of Exynos SoC to the Exynos Auto V9.
  • Unit and integration tests should be created and taken to completion by module owners.
  • Enable virtualization support for different hypervisors and devices in the final solution consisting of various VMs.
  • Upgrade existing drivers and enable PoC scenarios as per customer needs.
  • Create and regularly update design documents, study reports, test reports and application notes for respective modules.
Apply Now

Firmware Developer

Location : Bangalore

Experience: 3 to 10 Years

Requirements & Skillset: All engineers should be well versed with Linux and QnX device driver and middleware frameworks for the following modules:

  • Multimedia: MIPI-CSI, Image capture and processing IP, Scalars, H/W Video codec acceleration (typically MFC for exynos), ALSA and other audio driver layers.
  • System Interface: System bring-up, USB, Ethernet, UFS, PCIe.
  • Graphics: GPU, Display, HDMI.

Job Description

  • All engineers will be required to develop device drivers as listed above, compatible with QnX RTOS on Samsung’s Exynos Auto V9 SoC.
  • Each device driver owner should be able to understand the Linux framework for their respective IPs and migrate the drivers to QnX.
  • Each device driver owner should be able to migrate or port QnX drivers from older version of Exynos SoC to the Exynos Auto V9.
  • Unit and integration tests should be created and taken to completion by module owners.
  • Enable virtualization support for different hypervisors and devices in the final solution consisting of various VMs.
  • Upgrade existing drivers and enable PoC scenarios as per customer needs.
  • Create and regularly update design documents, study reports, test reports and application notes for respective modules.
Apply Now

Engineer (3+ years of experience in FreeRTOS & good knowledge on Linux Background )

Qualification: BE/B.Tech, ME/M.Tech

Location : Bangalore

Positions: 3

Requirements & Skillset

  • A self-motivated Software Engineer (3+ Years of Experience in Embedded SW Development).
  • Strong C programming skills and hands-on development experience in Linux & FreeRTOS platform.
  • Should Have Good understanding on all Embedded protocols like UART, SPI, USB & I2C.
  • Should Have experience in Board Bring-up activities.
  • Better to have knowledge on Bare-Metal programming skills.
  • Should have experience in ARM/PPC/x86 processor platforms.
  • Should have work experience on 16/32-bit Microcontroller.
  • Should have experience in developing USB drivers in Linux.
  • Good to have knowledge on DSP’s Processor.
  • Should have experience in using Altera based development flow particularly Quartus, SOPC build & SOC EDA tools.
  • Strong in communication and customer interaction with right attitude.

Responsibilities

  • Understand complete requirements from customer and translate them it into SW implementable modules for the HW / OS platforms.
  • Responsible for designing, developing, and implementing embedded SW systems and track the SW Development schedule.
  • The job involves device level debug and bring up in co-ordination with Cross functional Teams.
Apply Now

Sr. Test Engineer – Post Silicon Validation & Characterization (HSIO)

Qualification: BE/B.Tech, ME/M.Tech

Location : Bangalore

Positions: 5

Requirements

  • Proven experience in deriving test plan based on chip data sheet, test board HW design, test automation with min of 5 to 6 Years of Experience.
  • Proven experience in bench test of High-Speed IP Modules / Controller based SOCs with popular high-speed interface standards such as DDR2/DDR3/SATA/MIPI-MPHY/MIPI-DPHY/CSI/USB2.0/USB3.0/PCI-e etc.
  • Working experience in bring up of Complex Boards and preparation of Bench Test Setup with high end equipment.
  • Strong Electrical engineering fundamentals with ability to identify suitable test equipment & test methodology requirement to perform Post Si Validation and Characterization.
  • Experience in using / controlling basic lab equipments like Oscilloscopes, Spectrum analyzers, clock and timing sources, signal generators etc.
  • Exposure on Lab Automation tools (LabVIEW) / Python / other scripting languages – highly desirable.
  • Ability to write SW macros / Test script to program SOC module – a major plus.
  • Exposure on FPGA Design Tools such as Xilinx / Altera – added advantage but not desired.
  • Good mentoring, Communication Skill and Team work.
  • Ability to work as an independent contributor & a team player at customer site; Coordinate with designers on-site to ensure meet characterization schedule.

Responsibilities

  • To get involved in understanding new requirements from Design Team, participate in the Technical discussions and prepare test, debug and compliance reports as per customer requirement.
  • To participate in design, development and implementation of cost-effective methods of testing and troubleshooting systems and equipment.
  • Prepares test and diagnostic programs, designs test fixtures & carry out complete Electrical Characterization and Debug of the device.
  • The job involves device level debug and bring up, co-ordination with Equipment vendors, Lab Characterization of the device developed, Device programming / testing new device samples for customers etc.
Apply Now

Sr. Test Engineer – Post Silicon Validation & Characterization (Analog)

Qualification: BE/B.Tech, ME/M.Tech

Location : Bangalore

Positions: 5

Requirements

  • Proven experience in deriving test plan based on chip data sheet, test board HW design, test automation with min of 6 to 7 Years of Experience.
  • Proven experience in bench test of analog devices / IP Modules like Data Converters, Analog Front End (AFE), Analog filters, LDO, switching converters and Band gap Reference.
  • Strong Analog Domain Experience preferred.
  • Strong Electrical engineering fundamentals with ability to identify suitable test equipment & test methodology requirement to perform Post Si Validation and Characterization.
  • Experience in using / controlling basic lab equipment like Oscilloscopes, Spectrum analyzers, clock and timing sources, signal generators etc.
  • Exposure on Lab Automation tools (LabVIEW) / scripting languages – highly desirable.
  • Should be able to understand Processor based SOCs and ability to write SW macros to program SOC module.
  • Exposure on FPGA Design Tools such as Xilinx / Altera is a major plus but not desired.
  • Good mentoring, Communication Skill and Team work.
  • Ability to lead a highly motivated team of 3 to 4 engineers and represent the team at customer site; Coordinate with designers on-site to ensure meet characterization schedule.

Responsibilities

  • Responsible for designing, developing, and implementing cost-effective methods of testing and troubleshooting systems and equipment.
  • Prepares test and diagnostic programs, designs test fixtures & carry out complete Electrical Characterization and Debug of the device.
  • Mentoring Junior Engineers and identify Training Requirements for the team members.
  • The job involves device level debug and bring up, co-ordination with Equipment vendors, Lab Characterization of the device developed, Device programming / testing new device samples for customers etc.
  • To get involved in understanding new requirements from Design Team, participate in the Technical discussions and prepare test, debug and compliance reports as per customer requirement.
Apply Now

Software Engineer

Qualification: BE (CSE / IT) / MCA

Location : Vizag

Positions: 1

Notice Period: 1 Month

Responsibilities

  • As a Senior Software Engineer – you will contribute to analysis, design & development of features, creation of work plans.
  • You must be able to understand the requirements, existing features, design and architect solutions.
  • You will have opportunity to learn and implement both existing and new technologies, especially Digia Qt and C++/C# on Windows platform.

Experience

  • 1+ years of hands-on experience on ‘Digia Qt’.
  • 1+ years of hands-on experience on ‘C++’ or ‘C#’.
  • Should have development experience on Windows Application and DLL.
  • Ability to design and develop independently follow development processes, reviews and integration to handle releases.
  • Strong ability to understand existing code and create quality code from design models/documents.
  • Good understanding of object oriented design and knowledge of product life cycles.
  • Experience with any ATE test systems highly desirable.

Additional Skills

  • Programming knowledge on VBA, Python, MATLAB & Perl.
  • ATE – Pattern Conversion tool development experience.
  • Digital logic basics.
Apply Now

Senior Software Engineer

Qualification: BE (CSE / IT) / MCA

Location : Bangalore

Positions: 1

Notice Period: 1 Month

Responsibilities

  • As a Senior Software Engineer – you will contribute to analysis, design & development of features, creation of work plans.
  • You must be able to understand the requirements, existing features, design and architect solutions with junior engineers with you.
  • You will have opportunity to learn and implement both existing and new technologies, especially Digia Qt and C++/C#.

Experience

  • 3+ years of ‘C++’ expertise in designing and developing solutions.
  • 1+ years of ‘C#’ expertise in designing and developing solutions.
  • 3+ years of ‘Digia Qt‘ expertise in designing and developing solutions.
  • Application Deployment – Visual Studio, Install Shield.
  • Prefer to have Cross Platform Compilation experience.
  • Should have ‘Windows Application’, ‘STL’ and ‘Windows DLL’ development experience.
  • Ability to design and develop independently follow development processes, reviews and integration to handle releases.
  • Strong ability to understand existing code and create quality code from design models/documents.
  • Good understanding of object oriented design and knowledge of product life cycle.
  • Experience with any ATE test systems highly desirable.
  • Should have prior experience in developing solution by managing couple of junior engineers working under you.

Additional Skills

  • Programming knowledge on Java, VBA, Python, MATLAB & Perl.
  • Experience in using Static Code Analysis tools.
  • ATE – Pattern Conversion tool development experience.
  • Digital logic basics.
Apply Now

Sr. Engineer (5-7 years of experience in Linux Application Development Background)

Qualification: BE / B.Tech

Location : Bangalore

Positions: 2

Requirements

  • A self-motivated Senior Software Engineer (5 to 7 Years of Experience in Embedded SW Development).
  • Strong C / C++ programming skills and hands-on development experience in Linux platform.
  • Must to have Good experience in Docker container.
  • Must to have knowledge on open source tools & libraries.
  • Should Have Good experience in yocto build.
  • Should Have Good experience in xilinx petalinux tools.
  • Should Have Good understanding in Kernel Internals, Middleware, Abstraction & Application layer.
  • Should Have Good knowledge in Device Drivers (PCIE & Char).
  • Linux Kernel development with extensive experience in ARM/x86/PPC Architecture.
  • Knowledge on Sata and PCI NVME interface.
  • Should have knowledge on ARM mali usage on xilinx fpga.
  • Should have Knowledge on VCU block and GStreamer framework.
  • Should have experience on Xilinx DPU IP and support for AI framework like Caffe and Tensorflow.
  • Should have knowledge on Precision timebased protocol PTP1588.
  • Device driver development, Driver adaption, porting, enhancing & fine tuning the Kernel.
  • Development knowledge on BSP is must.
  • Knowledge on Boot architecture U-Boot & GRUB.
  • Knowledge on Kernel debugging tools like JTAG/T32/GDB.
  • Good mentoring, Communication Skill and team build capabilities / Management
  • Strong in communication and customer interaction with right attitude

Responsibilities

  • Understand complete requirements from customer and translate them it into SW implementable modules for the HW / OS platforms.
  • Responsible for designing, developing, and implementing right embedded SW systems and track the SW Development schedule.
  • To co-ordinate with Program Managers / Customers on-site and participate in discussions related to new projects.
  • The job involves device level debug and bring up in co-ordination with Cross functional Teams.
Apply Now

FPGA RTL Engineer (4+ years of experience in FPGA RTL development and RTL porting/Testing)

Qualification: BE / B.Tech

Location : Bangalore

Positions: 1

Requirements / Skill

  • RTL(VHDL/VERILOG) Coding & Design for real-time digital systems using Complex FPGAs and SOC FPGAs (Altera and Xilinx).
  • Experienced in Xilinx Vivado and Altera Quartus Tools.
  • Experienced in IP porting and usage like DDR3 (MIG), PCIe, SRIO, ETH, UART etc…
  • Work experienced in any High speed Interface like PCIe, DDR3, ETH and experienced in SPI, I2C, UART protocols.
  • Knowledge required in Pin assignments & Timing constraints/Timing Verification.
  • Understanding of Design Flow & Tool flow on each stage of RTL cycle & Board level testing cycle.
  • Carried out the Real-Time Board bringup & testing activities for FPGA interfaces, able to understand schematics and board files.
  • Should be able to Closely work with Software Engineers and System Engineers.
  • Define working parameters and output and input processes for FPGA & Logical thinking required.
  • Coordinate the development of subsystems modules & Perform FPGA system integration of all subsystems.
  • Implement test strategies for top level and module level test environments & Verify system designs are in compliance with performance and functional requirements.
  • Documenting knowledge required for FPGA design logic & Specifications.
  • Knowledge of RTOS such Linux and Robotic OS is plus point.
Apply Now

Sr. Engineer (5-7 years of experience in Linux Application Development Background)

Qualification: BE / B.Tech

Location : Bangalore

Positions: 2

Requirements

  • A self-motivated Senior Software Engineer (5 to 7 Years of Experience in Embedded SW Development).
  • Strong C / C++ programming skills and hands-on development experience in Linux platform.
  • Must to have Good experience in Docker container.
  • Must to have knowledge on open source tools & libraries.
  • Should Have Good experience in yocto build.
  • Should Have Good experience in xilinx petalinux tools.
  • Should Have Good understanding in Kernel Internals, Middleware, Abstraction & Application layer.
  • Should Have Good knowledge in Device Drivers (PCIE & Char).
  • Linux Kernel development with extensive experience in ARM/x86/PPC Architecture.
  • Knowledge on Sata and PCI NVME interface.
  • Should have knowledge on ARM mali usage on xilinx fpga.
  • Should have Knowledge on VCU block and GStreamer framework.
  • Should have experience on Xilinx DPU IP and support for AI framework like Caffe and Tensorflow.
  • Should have knowledge on Precision time based protocol PTP1588.
  • Device driver development, Driver adaption, porting, enhancing & fine tuning the Kernel.
  • Development knowledge on BSP is must.
  • Knowledge on Boot architecture U-Boot & GRUB.
  • Knowledge on Kernel debugging tools like JTAG/T32/GDB.
  • Good mentoring, Communication Skill and team build capabilities / Management.
  • Strong in communication and customer interaction with right attitude.

Responsibilities

  • Understand complete requirements from customer and translate them it into SW implementable modules for the HW / OS platforms.
  • Responsible for designing, developing, and implementing right embedded SW systems and track the SW Development schedule.
  • To co-ordinate with Program Managers / Customers on-site and participate in discussions related to new projects.
  • The job involves device level debug and bring up in co-ordination with Cross functional Teams.
Apply Now

Lead Test Engineer – Analog & Mixed Signal

Location : Visakhapatnam, AP, India.

Functional Area: Post Silicon Validation

Preferred Tester Platform: Teradyne Uflex and Advantest 93K – Analog and Mixed Signal Test Experience

Requirements

  • B. Tech /BS/MS in Electronics Engineering or equivalent.
  • 5 – 10 years’ experience in Semiconductor testing and post silicon validation for complex Mixed Signal/power management devices.
  • Strong knowledge in Analog Electronics fundamentals, able to analyze analog circuits like current mirrors, Band gap references, LDO, Buck, Boost, Oscillators, Battery chargers etc.
  • Strong knowledge in ATEs like Advantest 93K/Teradyne Flex/LTXC. Preferred tester platform is Advantest 93k.
  • Sound knowledge on Analog and Mixed Signal test methodologies.
  • Experience in developing the test program in ATE environment for Digital, Mixed Signal and Power Management devices.
  • Ability to work with common lab equipment such as power supplies, oscilloscopes, spectrum analyzers, logic analyzers, JTAG debugger, frequency counters, etc.
  • Exposure to test development & understanding the Circuit schematic is an added advantage. Extensive exposure on debug of Mixed signal/Power management devices using ATE tools and bench equipment.
  • Knowledge on ATE hardware design (load board, probe cards), PCB design tools and signal integrity analysis.
  • Proven Ability in Customer communication and interaction.
  • Knowledge on DFT and bench testing will be an added advantage.
  • Knowledge on device characterization and production release qualification process.
  • Experience in test program release procedure at production test house.

Responsibilities

  • Work with design/DFT team to develop the detailed test procedure from device data sheet.
  • Design and develop the required test hardware- Load board, bench board, Qualification board and probe card.
  • Test program development of analog, mixed signal modules such as Buck/Boost/Buck-boost/LDOs, precision references, battery charge controllers, ADC, DAC etc.
  • Develop and debug ATE test program code in C++ and VB languages.
  • First silicon verification and device bring up using ATE tools and bench equipment.
  • Device characterization across temperature, voltage and process corners and validate the chip against the specification.
  • Responsible for releasing the Final production quality test program to the customer – both wafer sort and final test program.
  • Interactions with the Design/DFT team throughout the project execution.
  • Interact with the customer on a daily basis and provide status update through e-mails and conference calls.
  • Able to initiate and execute projects independently and should be a team player.
  • Able to mentor and lead a team to develop turn-key test solutions.
  • Responsible from the beginning to Final/Wafer sort Test program release at customer site.
Apply Now

Package Design Engineer

Experience: 1 – 6 yrs

Location: Bangalore

Job Responsibilities

  • Able to drive Package substrate designs – both wirebond and flip chip technologies for best possible electrical performance.
  • Define Package level Electrical, Assembly and foundry Design rules for each package type and be able to provide guidelines to Layout teams to meet those specifications.
  • Support feasibility studies for various package options based on product type.
  • Interact with die design teams to bump and pin placements.
  • Interact with customers and other stakeholders to recommend package solutions to meet customer and/or market requirements.
  • Provide design support for thermal/mechanical/electrical simulation analysis.

Substrate Designs

  • Able to drive substrate design stages – die and package creation, wirebond definitions, DRC set up, Bga net Assignment, power partitions, routing closure, design guides implementation with respect to the interfaces used.
  • Generate all required outputs/deliverables with respect to the customer,manufacturer and assembler requirements.
  • To perform design reviews in a timely and efficient manner

Documentation

  • Familiarity with documentation work flows and signoff flows.
  • Provide accurate Manufacturing Drawings, Package Outline Drawings, Interposer Drawings, and WireBond Diagrams.
Apply Now

Test Engineer / Sr Test Engineer / Lead Engineer

Experience: 3 – 8 yrs

Location: Bangalore – INDIA

Job ID: ATEB12020

Job Description

  • Test program development on complex Analog/Power/Mixed Signal devices.
  • Involve in various conversion / NPI projects & Responsible to bring up devices on new platform.
  • Quoting the JOB ID is mandatory while applying for this job opening.

Job Requirement

  • 3-8 years of experience in the Semiconductor Analog/ Power ATE domain as a Test, Product Engineer is mandatory.
  • Familiar with Semiconductor Product Test Development process and procedures in the wafer sort and/or Final test environments.
  • Demonstratable Analog /Power management product debugging , Test program development skills in ATE like FLEX series / ETS series, ASK1K , Advantest T2K/ V93K-PAC , LTXC series Tester platforms is highly preferred.
  • Good Programming skills and demonstratable good programming practices are highly desired.
  • Demonstratable experience for leads in the fields of Design tester hardware (Probe Card and Loadboard) for Medium to complex Analog/ Power management Devices, Create test plans , architecture and test methodologies to meet Product test Specifications is desired.
  • Able to work independently with minimum guidance and with good initiative to overcome technical challenges in the areas of test S/W & H/W development and product bring up onsite is highly desirable.
  • Familiar with the use of all common electronic bench equipment like oscilloscope, DMM, logic analyser and ATE debug tools efficiently a must.
  • University Engineering Degree/ Diploma in Electrical / Electronic discipline with a basic understanding of Analog / Digital electronics fundamentals and circuit theory is a must.
  • Good verbal and written communication skill is expected.
  • Candidates with relevant ATE experience only need to apply.
Apply Now

Test Engineer / Sr Test Engineer

Experience: 2+ yrs

Location: Singapore

Job ID: ATES12020

Job Description

  • Test program development on complex Automotive Analog/Power/Mixed Signal devices.
  • Involve in various conversion / NPI projects & Responsible to bring up devices on new platform.

Job Requirement

  • Job opening considered only for Singapore Citizen or Singapore PRs.
  • 2 + years of experience in the Semiconductor Analog/ Power ATE domain as a Test, Product Engineer.
  • Familiar with Semiconductor manufacturing process and procedures in the wafer sort and/or Final test environments.
  • Demonstratable Analog /Power management product debugging skills , Test program development in ATE like FLEX series / ETS series, ASK1K , Advantest T2K, LTXC series Tester platforms is highly preferred.
  • Able to work independently with minimum guidance and with good initiative to overcome technical challenges in the areas of test development and product bring up at initial ramp stage is a must.
  • Familiar with the use of all common electronic bench equipment like oscilloscope, DMM, logic analyser.
  • University Engineering Degree/ Diploma in Electrical / Electronic discipline with a basic understanding of Analog electronics fundamentals and circuit theory is a must.
  • Good verbal and written English communication skill.
  • Higher experience candidates will be considered for Sr positions.
Apply Now

Physical Design _Full Chip Design (Automotive Domain Expert)

Experience: 7 to 18 years

Education: Any Engineering Degree or equivalent practical experience.

No Of Position: 1

Location: Bangalore

Job Description:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs ( Preferably below 28 Nm like 16/14/12/7 nm).
  • Experienced in leading SOC timing closure and physical design tasks with deep technical knowledge in all.
  • Experienced in Full Chip PNR & Partitioning / Bump Placement.
  • stages of the design (floor planning, placement, clock-tree-syntheses CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
  • Experience in Low power and high performance design.
  • Experience in designing for Automotive industry.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements.
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Expert in tools Cadence Encounter/ Magma Talus/Synopsys ICC / Cadence Innovus.

Experience:

  • Full Chip SOC.
Apply Now

Physical Design

Experience: 4 to 8 Years

Education: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

No. Of Positions: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Job Description:

  • Ability to handle the complete physical design and analysis of multiple designs independently.
  • Good understanding of the static timing analysis and experience of closing timing requirements on multiple designs.
  • Experience of closing power analysis (IR/EM), equivalency checks as well as low power checks.
  • Ability to run the physical verification as well as fix all the violations independently.
  • Exposure to the challenges in the physical design of chips targeted to 28nm/16nm / 7nm technology.
  • Experience in writing scripts using standard scripting languages (TCL/Perl).
  • Good communication skills.
  • 4 years of experience in physical design.
  • The job will involve working on multiple block level designs to close all the implementation, timing, power, and physical verification-related issues.
  • The candidate is also expected to contribute to the chip level analysis runs and solve some of the complex issues in the design.
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Physical Design Expert - SOC/IP/Sub-System Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 15 years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs (28/14/7nm) and associated issues (manufacturability, power, signal integrity, scaling).
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all.
  • Stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
  • Experience in Low power and high performance design.
  • Experience in designing for automotive industry.
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements.
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
  • Good understanding of mixed-signal building blocks.
  • Understanding of power management and its implication on physical design.
  • Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS.

Experience:

  • SOC/IP/Sub-System Design.
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DFT Engineer

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • The person hired in to this role will be contributing to DFT insertion and validation effort of complex DSP core.
  • In depth knowledge of DFT concepts.
  • In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
  • In depth knowledge and hands on experience in MBIST insertion and Memory test validation.
  • Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
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DFX / DFT Architect

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Preference: Candidate from semiconductor back ground

Requirements:

  • Strong knowledge of DFT architectures & methodologies. This includes Scan, BScan, IO DFx, analog DFT, JTAG, Boundary scan, etc with minimum experience of 4+ years.
  • Proven knowledge of Verilog , RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology (Synopsis VCS* and Verdi, Lintra, Spyglass, Tessent ATPG tools, Synopsys ATPG tools, etc).
  • Strong Si debug skills, ATE requirements and understanding of volume test requirements. Strong Communications skills and the ability to effectively work with cross functional teams across geographies.
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ASIC Synthesis

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 6+

Location: Bangalore

Requirements:

  • Good understanding of VHDL or System Verilog.
  • Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation.
  • Development of signoff quality SDC constraints and the development of power intent constraints.
  • May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.
  • Hands-on with Synopsys DC/DCT/DCG/DE-Explorer.
  • Hands-on with Synopsys Prime Time including SDC constraint development for complex blocks with many clock domains.
  • Hands-on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
  • Experience with either RTL development or Physical Design is also a plus.
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Synthesis/STA

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 12 years

No of Position: 4 (Lead / Experts)

Location: Bangalore

Requirements:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues.
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure with deep technical knowledge in all.
  • Stages of the design – functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Experience in Low power and high performance design.
  • Experience in designing for automotive industry.
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements.
  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
  • Good understanding of mixed-signal building blocks.
  • Understanding of power management and its implication on synthesis/STA.
  • Expert in tools – any vendor.
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RTL Design / Integrations

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 5+

Location: Bangalore

Requirements:

  • Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores.
  • Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation.
  • Demonstrated success in completing projects using high-speed logic design.
  • Experience with synthesis, Lint, CDC, and LEC.
  • Knowledge of protocols such as PCI-Express, RapidIO, NVM Express and LP DDR2/LP DDR3.
  • Candidate must have excellent Verilog and System Verilog concepts, and experience in verification of complex RTL designs and validating them on the boards is an added advantage.
  • Working knowledge of UNIX environment and scripting languages (PERL, Python/TCL etc) desired.
  • Strong analytical skills with attention to detail.
  • Excellent written & verbal communications skills.
  • Very good leadership skills.
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Lint / CDC / Synthesis

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4+

Location: Bangalore

Requirements:

  • Synthesis Constraints development, LINT checks, CDC checks.
  • Working / leading full-chip STA closure, defining mode requirements & corners for timing closure.
  • Formal Verification-Synopsys Formality/ Cadence.
  • CTS & ECO cycle.
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FPGA Emulation

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 4+

Location: Bangalore

Requirements:

  • Creates Emulation models from RTL design using Emulation tools.
  • Strong expertise into Emulation with Palladium, Veloce platforms at least one of them.
  • Should have good knowledge in implementing Bigger designs in multiple FPGA’s/HAPS platforms.
  • Familiarity with FPGA synthesis.
  • Working knowledge XILINX Virtex FPGA architecture and experience with ISE tool flow.
  • Good Knowledge of protocols: AXI/AHB, bridges, memory controllers such as DDR/Nand, and peripherals such as USB, PCIe, USB, &, Memory.
  • Good programming skills i.e. Verilog, VHDL, SV, C/C++ is a must.
  • Knowledge of Virtex or Kintex UltraScale is a definite plus.
  • Good written and oral communications skills required.

Experience:

  • Latest FPGAs Virtex-7 or Kintex-7 and above.
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SOC/ IP Verification

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 10 (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • The ideal candidate should be a hands-on expert in verification using System Verilog and have hands-on expertise in utilizing modern verification methodologies like VMM/UVM/OVM, to be part of the verification team of core IPs and complex subsystems with 4+ yrs. of experience.
  • Experience with verification methodologies such as UVM/VMM/OVM is required, and a strong understanding of UVM is preferred. Candidates are expected to have designed and developed UVM, SVTB and have previously composed functional coverage assertions, preferably using System Verilog.
  • Proficient on protocols – PCI-Express, RapidIO, NVM Express, LP DDR2/LP DDR3, AXI, AHB, USB, HDMI, MIPI, & ethernet.
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Memory Circuit Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4

Location: Bangalore

Requirements:

  • Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF Technologies.
  • Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
  • Development of critical path and characterization flow to perform detailed margin and characterization simulations.
  • Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off.
  • Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
  • Logic simulations and detailed timing analysis of key paths in high speed memory design.
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IO Layout

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 3 to 8 years

No of Position: 2

Location: Bangalore

Requirements:

  • Good Knowledge about IO Layout, should have work experience on 28nm (Below 28nm is highly preferable).
  • Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS.
  • Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation in Layout Design.
  • Sound knowledge of IO blocks like Design of the Transmitter /Receiver Blocks, Level Shifters.
  • Exposure to DDR IOs, XTAL IOs an added advantage.
  • Very Good CMOS fundamental.
  • Good Communication Skill.
  • Skill/Perl programming knowledge is an added advantage.
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Analog Circuit Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 6

Location: Bangalore

Requirements:

  • Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
  • Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
  • Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
  • High Speed Latch,High Speed Rx Front End.
  • Must understand Solid state physics, Short Channel Effects, Lower Process node trade-offs,K-MAP, Boolean Algebra.
  • Must understand Matching Device Concepts,ESDS,Latup, Antenna effect, Modeling spice/AMS.

Good to have:

  • Must have worked on atleast one of the Block Design with Full Ownership.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • Power Management Blocks such as LDO, Buck Boost,Switching Regulator for more than 1A regulated Output Current.
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Analog Layout Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 6

Location: Bangalore

Requirements:

  • Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
  • Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
  • Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
  • High Speed Latch,High Speed Rx Front End.
  • Must understand Fabrication steps, short channel effects, EM, IR Drop, RV Violations.
  • Must understand Matching Device Concepts, ESDS, Latup, Antenna effect, Common Centroid, Interdigitized Matching Tradeoffs.

Good to have:

  • Must have worked on atleast one of the Layout Block with Full Ownership.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • Power Management Layout Blocks such as LDO, Buck Boost, Switching Regulator for more than 1A regulated Output Current.
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AMS Verification

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4

Location: Bangalore

Requirements:

  • Experience in Analog and Mixed Signal (AMS) verification.
  • Hands-on experience in C/C++ based verification and SV/UVM based verification.
  • Strong fundamental knowledge of analog circuits behavior.
  • Ability to write models using Verilog/Verilog-AMS.
  • Understanding complete verification flow.
  • Experience in SV/PSL assertion methodology.
  • Hands-on experience on Cadence and other tool flows.
  • Gate level simulation experience is an advantage.
  • Good Communication skills.
  • Strong problem solving and analytical skills.
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Layout Design Engineer

Qualification: BE/ME in ECE/EEE

Experience: 3+ Years

Requirements:

  • Substrate layout design, cadence tools
  • PCB routing,Library creation, RDL routing, simulations
  • Substrate material knowledge is added advantage

Responsibilities:

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IP/SoC Logic Design Engineer

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 – 15 years

No of Position: 3

NOTE: This is for ONSITE to US and Valid H1B VISA is Mandatory

Job Description:

  • Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs
  • Participates in the development of Architecture and Microarchitecture specifications for the Logic components
  • Evaluates new feature requests, Designs and develops IP features
  • Provides IP integration support to SoC customers and represents RTL team
  • Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design

Responsibilities:

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