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Takes Wings At Tessolve

Careers

Why join Tessolve?

At Tessolve, we help individuals realize their full potential, fostering excellence with our wholesome working environment. To our employees, we bring exposure to latest technology, and an opportunity to explore the application of silicon engineering across a wide breadth of industries. It means, you have the chance to work with globally diverse customers on cutting edge engineering projects while growing with a top tier company that is a pioneer in hardware testing.

You are welcome to – Join the Tessolve family.

Join Us

If you are –

Work Benefits

Perks of being at Tessolve

  • Compressed work week
  • Transport assistance
  • Provision for lunch, coffee and tea on-site
  • Enrollment to Employee Provident Fund scheme
  • Medical insurance for employees and dependents
  • Gratuity scheme for employees working 5 years and beyond
  • Attractive monthly Earned Leave credits and accrual limits
  • Flexible work options for certain cases and situations
  • On-site gym, TT table, and so much more

The Tessolve Worklife

Not work but growth as it should be

Open Positions

We are ready for you. Are you too?

Software Engineer

Qualification: BE/B.Tech, ME/MTech in Computer Science/Electrical/Electronics

Experience: 2 – 4 yrs

Location: Bangalore

No of Positions: 1

Job Responsibilities

  • As a Software Engineer – you will contribute to the analysis, design & development of features, creation of work plans.
  • You must be able to understand requirements, existing features, design and architect solutions.
  • You will have opportunity to learn and implement both existing and new technologies.

Skills & Experience

  • 2+ years of ‘Python/Java’ expertise in designing and developing solutions.
  • 1+ years of hands-on experience in ‘MySQL’ Database solutions.
  • Demonstrated experience in Software Tool development preferably in ATE Test Engineering or other VLSI domain.
  • Familiarity with good software practices (Coding standard/validation).
  • Should have prior experience with GIT version control system.
  • Ability to design and develop independently follow development processes, reviews and integration to handle releases.
  • Strong ability to understand existing code and create quality code from design models/documents.
  • Good understanding of object oriented design and knowledge of product life cycles.
  • Experience with any ATE test systems highly desirable.
  • Should have worked on both LINUX and Windows platforms.

Additional Skills

  • Programming knowledge on C#/VBA/Perl.
  • ATE – Pattern Conversion tool development experience.
  • Digital logic basics.
Apply Now

Electrical Validation Engineer

Experience: 1 – 6 yrs

Location: Bangalore

No of Positions: 2

Job Requirements

  • Able to Develop and document electrical validation requirements and tests for verification of Si/HW designs.
  • Able to Create, define and develop Electrical validation environment and test suites. Use and apply emulation and platform level tools and techniques to ensure performance to spec.
  • Responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future debug features.

Job Responsibilities (Included but not limited to the following)

  • Validate DCPMM (Crystal Ridge) on Intel’s next generation servers.
  • Evaluate and debug platform memory failures using logic analyzer, oscilloscope, and other EV tools.
  • Work in Validation, System Debug, Power & Signalling work groups to resolve sightings.
  • Collaborate with internal hardware design teams to evaluate signaling of test hardware designs.
  • Create system validation test plans based on DCPMM memory design specifications.
  • File HSD sightings and work with other Intel validation teams to resolve before PR.
  • Should demonstrate leadership in ability to lead and drive engineering solution with stakeholder.
  • Post Si EV knowledge in any field of Bench Design Validation, Signal Integrity Validation, or System Margining Validation.
  • Familiar with validation technique and electrical compliance requirement.
  • Preferably with 3-7 years of experience in electrical validation using Intel platforms.
  • Experience with logic analyzer, oscilloscopes, BERT, ITP, Lauterbach, sigtest eye diagram tool or related electrical validation test equipment is required.
  • Experience in scripting for debug and automation needed, preferably Python or SVOS.
  • Experience working with DDR or DCPMM memory in Intel systems (Good to have).
Apply Now

Package Design Engineer

Experience: 1 – 6 yrs

Location: Bangalore

Job Responsibilities

  • Able to drive Package substrate designs – both wirebond and flip chip technologies for best possible electrical performance.
  • Define Package level Electrical, Assembly and foundry Design rules for each package type and be able to provide guidelines to Layout teams to meet those specifications.
  • Support feasibility studies for various package options based on product type.
  • Interact with die design teams to bump and pin placements.
  • Interact with customers and other stakeholders to recommend package solutions to meet customer and/or market requirements.
  • Provide design support for thermal/mechanical/electrical simulation analysis.

Substrate Designs

  • Able to drive substrate design stages – die and package creation, wirebond definitions, DRC set up, Bga net Assignment, power partitions, routing closure, design guides implementation with respect to the interfaces used.
  • Generate all required outputs/deliverables with respect to the customer,manufacturer and assembler requirements.
  • To perform design reviews in a timely and efficient manner

Documentation

  • Familiarity with documentation work flows and signoff flows.
  • Provide accurate Manufacturing Drawings, Package Outline Drawings, Interposer Drawings, and WireBond Diagrams.
Apply Now

Test Engineer / Sr Test Engineer / Lead Engineer

Experience: 3 – 8 yrs

Location: Bangalore – INDIA

Job ID: ATEB12020

Job Description

  • Test program development on complex Analog/Power/Mixed Signal devices.
  • Involve in various conversion / NPI projects & Responsible to bring up devices on new platform.
  • Quoting the JOB ID is mandatory while applying for this job opening.

Job Requirement

  • 3-8 years of experience in the Semiconductor Analog/ Power ATE domain as a Test, Product Engineer is mandatory.
  • Familiar with Semiconductor Product Test Development process and procedures in the wafer sort and/or Final test environments.
  • Demonstratable Analog /Power management product debugging , Test program development skills in ATE like FLEX series / ETS series, ASK1K , Advantest T2K/ V93K-PAC , LTXC series Tester platforms is highly preferred.
  • Good Programming skills and demonstratable good programming practices are highly desired.
  • Demonstratable experience for leads in the fields of Design tester hardware (Probe Card and Loadboard) for Medium to complex Analog/ Power management Devices, Create test plans , architecture and test methodologies to meet Product test Specifications is desired.
  • Able to work independently with minimum guidance and with good initiative to overcome technical challenges in the areas of test S/W & H/W development and product bring up onsite is highly desirable.
  • Familiar with the use of all common electronic bench equipment like oscilloscope, DMM, logic analyser and ATE debug tools efficiently a must.
  • University Engineering Degree/ Diploma in Electrical / Electronic discipline with a basic understanding of Analog / Digital electronics fundamentals and circuit theory is a must.
  • Good verbal and written communication skill is expected.
  • Candidates with relevant ATE experience only need to apply.
Apply Now

Test Engineer / Sr Test Engineer

Experience: 2+ yrs

Location: Singapore

Job ID: ATES12020

Job Description

  • Test program development on complex Automotive Analog/Power/Mixed Signal devices.
  • Involve in various conversion / NPI projects & Responsible to bring up devices on new platform.

Job Requirement

  • Job opening considered only for Singapore Citizen or Singapore PRs.
  • 2 + years of experience in the Semiconductor Analog/ Power ATE domain as a Test, Product Engineer.
  • Familiar with Semiconductor manufacturing process and procedures in the wafer sort and/or Final test environments.
  • Demonstratable Analog /Power management product debugging skills , Test program development in ATE like FLEX series / ETS series, ASK1K , Advantest T2K, LTXC series Tester platforms is highly preferred.
  • Able to work independently with minimum guidance and with good initiative to overcome technical challenges in the areas of test development and product bring up at initial ramp stage is a must.
  • Familiar with the use of all common electronic bench equipment like oscilloscope, DMM, logic analyser.
  • University Engineering Degree/ Diploma in Electrical / Electronic discipline with a basic understanding of Analog electronics fundamentals and circuit theory is a must.
  • Good verbal and written English communication skill.
  • Higher experience candidates will be considered for Sr positions.
Apply Now

Lab Technician

Experience: 2 – 4 yrs

Education: Diploma

Location: Bangalore

Job Description

  • Advantest 93k tester calibration and Diagnostic checks performed.
  • Advantest 93k tester and chiller, PCW, CDA daily monitoring.
  • Advantest 93k tester resources identification and error fixing.
  • Advantest RHEL software installation and periodic license renewal.
  • Advantest 93K Simulator setup.
  • Advantest P.M activities.
Apply Now

Test Engineer (Bench Characterization)

Experience: 1 – 5 yrs

Education: MTech, B.Tech or Equivalent in Electronics or Electrical Engineering

Location: Bangalore

Job Description

  • This group develops Test solutions for Design verification of Highly integrated SOCs ( System on Chip) designed by Qualcomm.
  • As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, Clocking architecture, Delay circuits, Power Distribution Network) and High Speed IO interfaces ( PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL ).
  • You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of DDR & High Speed IO IPs and perform failure analysis to root-cause a design problem.
  • You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment.

Preferred Qualifications

  • Candidate must be familiar with Test and characterization of DDR and High-Speed IO interfaces with in-depth understanding of Mobile & PC DDR 2/3/4 protocol, timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding).
  • Hands-on experience using Bench instruments (oscilloscopes, J-BERT, network / spectrum analyzers, signal generators, logic analyzers) is a must.
  • Required programming skills: C, C++, C-Sharp (or equivalent) and LabView.
  • Decent understanding of VLSI technologies, analog and digital integrated circuits, semiconductor physics.
  • Strong interpersonal, problem solving & debugging skills.
  • Need proven ability to work effectively in a fast-paced environment with strong verbal and written communication skills.
Apply Now

Purchase Assistant

Experience: 1 – 2 yrs

Education: Diploma in Electronics

Location: Bangalore

Job Description

  • BOM Costing with online cost.
  • PO release & follow up.
  • Getting the invoice on time and updating in the tracker.
  • PO Master Updation.
  • May need to visit suppliers for material followup-collection in case of emergency.
  • Other documentations like AVL updation, Vendor Rating using ERP data.
  • Followup with internal team for shipments delivery, quality clearance.
  • Preparation of Required reports
Apply Now

Physical Design _Full Chip Design (Automotive Domain Expert)

Experience: 7 to 18 years

Education: Any Engineering Degree or equivalent practical experience.

No Of Position: 1

Location: Bangalore

Job Description:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs ( Preferably below 28 Nm like 16/14/12/7 nm).
  • Experienced in leading SOC timing closure and physical design tasks with deep technical knowledge in all.
  • Experienced in Full Chip PNR & Partitioning / Bump Placement.
  • stages of the design (floor planning, placement, clock-tree-syntheses CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
  • Experience in Low power and high performance design.
  • Experience in designing for Automotive industry.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements.
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Expert in tools Cadence Encounter/ Magma Talus/Synopsys ICC / Cadence Innovus.

Experience:

  • Full Chip SOC.
Apply Now

Physical Design

Experience: 4 to 8 Years

Education: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

No. Of Positions: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Job Description:

  • Ability to handle the complete physical design and analysis of multiple designs independently.
  • Good understanding of the static timing analysis and experience of closing timing requirements on multiple designs.
  • Experience of closing power analysis (IR/EM), equivalency checks as well as low power checks.
  • Ability to run the physical verification as well as fix all the violations independently.
  • Exposure to the challenges in the physical design of chips targeted to 28nm/16nm / 7nm technology.
  • Experience in writing scripts using standard scripting languages (TCL/Perl).
  • Good communication skills.
  • 4 years of experience in physical design.
  • The job will involve working on multiple block level designs to close all the implementation, timing, power, and physical verification-related issues.
  • The candidate is also expected to contribute to the chip level analysis runs and solve some of the complex issues in the design.
Apply Now

Physical Design Expert - SOC/IP/Sub-System Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 15 years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs (28/14/7nm) and associated issues (manufacturability, power, signal integrity, scaling).
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all.
  • Stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
  • Experience in Low power and high performance design.
  • Experience in designing for automotive industry.
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the Physical Design requirements.
  • Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
  • Good understanding of mixed-signal building blocks.
  • Understanding of power management and its implication on physical design.
  • Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS.

Experience:

  • SOC/IP/Sub-System Design.
Apply Now

DFT Engineer

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • The person hired in to this role will be contributing to DFT insertion and validation effort of complex DSP core.
  • In depth knowledge of DFT concepts.
  • In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
  • In depth knowledge and hands on experience in MBIST insertion and Memory test validation.
  • Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
Apply Now

DFX / DFT Architect

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Preference: Candidate from semiconductor back ground

Requirements:

  • Strong knowledge of DFT architectures & methodologies. This includes Scan, BScan, IO DFx, analog DFT, JTAG, Boundary scan, etc with minimum experience of 4+ years.
  • Proven knowledge of Verilog , RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology (Synopsis VCS* and Verdi, Lintra, Spyglass, Tessent ATPG tools, Synopsys ATPG tools, etc).
  • Strong Si debug skills, ATE requirements and understanding of volume test requirements. Strong Communications skills and the ability to effectively work with cross functional teams across geographies.
Apply Now

ASIC Synthesis

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 15 Years

No of Position: 6+

Location: Bangalore

Requirements:

  • Good understanding of VHDL or System Verilog.
  • Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation.
  • Development of signoff quality SDC constraints and the development of power intent constraints.
  • May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.
  • Hands-on with Synopsys DC/DCT/DCG/DE-Explorer.
  • Hands-on with Synopsys Prime Time including SDC constraint development for complex blocks with many clock domains.
  • Hands-on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
  • Experience with either RTL development or Physical Design is also a plus.
Apply Now

Synthesis/STA

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 12 years

No of Position: 4 (Lead / Experts)

Location: Bangalore

Requirements:

  • Must be hands-on technical expert.
  • Strong written and oral communication skills.
  • Experienced in deep sub-micron designs (65/45/40/28/14nm) and associated issues.
  • Experienced in leading Hard-IP/HardMacro/SOC timing closure with deep technical knowledge in all.
  • Stages of the design – functional and test mode, core and IO constraints development, synthesis, optimization, STA setup with associated automation, cross-talk noise/dealy, STA signoff.
  • Experience in Low power and high performance design.
  • Experience in designing for automotive industry.
  • Be able and willing to mentor junior team members technical or otherwise.
  • Should be able to lead by example.
  • Be able to support periodic training session and knowledge sharing sessions.
  • Able and willing to work with teams across sites and with cross-functional teams.
  • Able to collaborate, extract information and deliver results.
  • Should have sound understanding of all the design requirements.
  • Should be able to comprehend architecture, architecture limitations from STA/Synthesis perspective, schedule, volume of the task and personnel requirement.
  • Strong debug skills and Automation savvy.
  • Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
  • Good understanding of mixed-signal building blocks.
  • Understanding of power management and its implication on synthesis/STA.
  • Expert in tools – any vendor.
Apply Now

RTL Design / Integrations

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 5+

Location: Bangalore

Requirements:

  • Responsibilities include RTL development, resolving system-level challenges, architecting, implementing, documenting and validating the memory controller IP cores.
  • Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation.
  • Demonstrated success in completing projects using high-speed logic design.
  • Experience with synthesis, Lint, CDC, and LEC.
  • Knowledge of protocols such as PCI-Express, RapidIO, NVM Express and LP DDR2/LP DDR3.
  • Candidate must have excellent Verilog and System Verilog concepts, and experience in verification of complex RTL designs and validating them on the boards is an added advantage.
  • Working knowledge of UNIX environment and scripting languages (PERL, Python/TCL etc) desired.
  • Strong analytical skills with attention to detail.
  • Excellent written & verbal communications skills.
  • Very good leadership skills.
Apply Now

Lint / CDC / Synthesis

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4+

Location: Bangalore

Requirements:

  • Synthesis Constraints development, LINT checks, CDC checks.
  • Working / leading full-chip STA closure, defining mode requirements & corners for timing closure.
  • Formal Verification-Synopsys Formality/ Cadence.
  • CTS & ECO cycle.
Apply Now

FPGA Emulation

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 4+

Location: Bangalore

Requirements:

  • Creates Emulation models from RTL design using Emulation tools.
  • Strong expertise into Emulation with Palladium, Veloce platforms at least one of them.
  • Should have good knowledge in implementing Bigger designs in multiple FPGA’s/HAPS platforms.
  • Familiarity with FPGA synthesis.
  • Working knowledge XILINX Virtex FPGA architecture and experience with ISE tool flow.
  • Good Knowledge of protocols: AXI/AHB, bridges, memory controllers such as DDR/Nand, and peripherals such as USB, PCIe, USB, &, Memory.
  • Good programming skills i.e. Verilog, VHDL, SV, C/C++ is a must.
  • Knowledge of Virtex or Kintex UltraScale is a definite plus.
  • Good written and oral communications skills required.

Experience:

  • Latest FPGAs Virtex-7 or Kintex-7 and above.
Apply Now

SOC/ IP Verification

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 10 (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

  • The ideal candidate should be a hands-on expert in verification using System Verilog and have hands-on expertise in utilizing modern verification methodologies like VMM/UVM/OVM, to be part of the verification team of core IPs and complex subsystems with 4+ yrs. of experience.
  • Experience with verification methodologies such as UVM/VMM/OVM is required, and a strong understanding of UVM is preferred. Candidates are expected to have designed and developed UVM, SVTB and have previously composed functional coverage assertions, preferably using System Verilog.
  • Proficient on protocols – PCI-Express, RapidIO, NVM Express, LP DDR2/LP DDR3, AXI, AHB, USB, HDMI, MIPI, & ethernet.
Apply Now

Memory Circuit Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4

Location: Bangalore

Requirements:

  • Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF Technologies.
  • Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
  • Development of critical path and characterization flow to perform detailed margin and characterization simulations.
  • Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off.
  • Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
  • Logic simulations and detailed timing analysis of key paths in high speed memory design.
Apply Now

IO Layout

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 3 to 8 years

No of Position: 2

Location: Bangalore

Requirements:

  • Good Knowledge about IO Layout, should have work experience on 28nm (Below 28nm is highly preferable).
  • Good Working Experience on Cadence Virtuoso LE/XL, Calibre/Assura/Hercules DRC, LVS.
  • Good Understanding of ESD/Antenna/Latch up/EM effects and their implementation in Layout Design.
  • Sound knowledge of IO blocks like Design of the Transmitter /Receiver Blocks, Level Shifters.
  • Exposure to DDR IOs, XTAL IOs an added advantage.
  • Very Good CMOS fundamental.
  • Good Communication Skill.
  • Skill/Perl programming knowledge is an added advantage.
Apply Now

Analog Circuit Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 12 years

No of Position: 6

Location: Bangalore

Requirements:

  • Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
  • Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
  • Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
  • High Speed Latch,High Speed Rx Front End.
  • Must understand Solid state physics, Short Channel Effects, Lower Process node trade-offs,K-MAP, Boolean Algebra.
  • Must understand Matching Device Concepts,ESDS,Latup, Antenna effect, Modeling spice/AMS.

Good to have:

  • Must have worked on atleast one of the Block Design with Full Ownership.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • Power Management Blocks such as LDO, Buck Boost,Switching Regulator for more than 1A regulated Output Current.
Apply Now

Analog Layout Design

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 6

Location: Bangalore

Requirements:

  • Minimum 3+ years of Design Knowledge in CMOS lower process nodes such as 7nm/14nm/28nm.
  • Should have worked on Basic Building Blocks Circuit Design of Analog such as Bandgap Reference.
  • Current Mirrors, Sample/Hold, Comparator, Differential Amplifier, Opamp, Bias Generator,POR/BOR.
  • High Speed Latch,High Speed Rx Front End.
  • Must understand Fabrication steps, short channel effects, EM, IR Drop, RV Violations.
  • Must understand Matching Device Concepts, ESDS, Latup, Antenna effect, Common Centroid, Interdigitized Matching Tradeoffs.

Good to have:

  • Must have worked on atleast one of the Layout Block with Full Ownership.
  • SerDes standards for one of the PCIe.X, SATA, CPRI, Fibre Transceiver.
  • High Speed DLL, PLL, CDR, ADC,DAC,USB1.1/USB2.0, OTG.
  • Power Management Layout Blocks such as LDO, Buck Boost, Switching Regulator for more than 1A regulated Output Current.
Apply Now

AMS Verification

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 4 to 8 years

No of Position: 4

Location: Bangalore

Requirements:

  • Experience in Analog and Mixed Signal (AMS) verification.
  • Hands-on experience in C/C++ based verification and SV/UVM based verification.
  • Strong fundamental knowledge of analog circuits behavior.
  • Ability to write models using Verilog/Verilog-AMS.
  • Understanding complete verification flow.
  • Experience in SV/PSL assertion methodology.
  • Hands-on experience on Cadence and other tool flows.
  • Gate level simulation experience is an advantage.
  • Good Communication skills.
  • Strong problem solving and analytical skills.
Apply Now

Layout Design Engineer

Qualification: BE/ME in ECE/EEE

Experience: 3+ Years

Requirements:

  • Substrate layout design, cadence tools
  • PCB routing,Library creation, RDL routing, simulations
  • Substrate material knowledge is added advantage

Responsibilities:

Apply Now

IP/SoC Logic Design Engineer

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 – 15 years

No of Position: 3

NOTE: This is for ONSITE to US and Valid H1B VISA is Mandatory

Job Description:

  • Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs
  • Participates in the development of Architecture and Microarchitecture specifications for the Logic components
  • Evaluates new feature requests, Designs and develops IP features
  • Provides IP integration support to SoC customers and represents RTL team
  • Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design

Responsibilities:

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