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Takes Wings At Tessolve

Careers

Why join Tessolve?

At Tessolve, we help individuals realize their full potential, fostering excellence with our wholesome working environment. To our employees, we bring exposure to latest technology, and an opportunity to explore the application of silicon engineering across a wide breadth of industries. It means, you have the chance to work with globally diverse customers on cutting edge engineering projects while growing with a top tier company that is a pioneer in hardware testing.

You are welcome to – Join the Tessolve family.

Join Us

If you are –

Work Benefits

Perks of being at Tessolve

  • Compressed work week
  • Transport assistance
  • Provision for lunch, coffee and tea on-site
  • Enrollment to Employee Provident Fund scheme
  • Medical insurance for employees and dependents
  • Gratuity scheme for employees working 5 years and beyond
  • Attractive monthly Earned Leave credits and accrual limits
  • Flexible work options for certain cases and situations
  • On-site gym, TT table, and so much more

The Tessolve Worklife

Not work but growth as it should be

Open Positions

We are ready for you. Are you too?

Sr Software Engineer - IoT Software-UI and Mobile Apps

Experience: 3+ years

Notice Period: Immediate/30 days

Location: Bangalore

Qualifications:

  • Bachelor/Master’s degree in Computer Science/Electronics or equivalent.
  • 3+ years Experience building UI for IoT devices applications.
  • Worked in an Agile environment.
  • Excellent coding skills in Javascript.
  • Good understanding of frameworks like Angular or React.
  • Past experience of data integration with Charts and Maps open javascript based frameworks.
  • Good experience in Software development practices and version control.
  • Experience with Android/iOS apps will be highly preferred.
  • Good communication skills enjoys interacting with customers, good team player and self-driven.

Mandatory Skills:

  • Experience in any of UI framework like Angular or React JS.
  • Hands-on in Javascript.
  • Hands-On in Mobile Apps Andriod or iOS.
  • Experience in Charts libraries.

Good to have skills:

  • Direct IoT application development experience.
Apply Now

PCB Design Engineer

Qualification: BE in ECE/EEE

Experience: 3 to 5 Years

No of Position: 1

Requirements:

  • Tools Expertise :
  • Orcad, Concept HDL
  • Cadence Allegro, Altium/Pads
  • Design Expertise :
  • Complete understanding of Constraint Manager Settings
  • High Speed Interfaces Exposure
  • HDI, Blind/Burried via technology Exposure
  • Individual Contributor Ability

Responsibilities:

  • Schematic Entry as per customer requirement
  • Component library creation as per JEDEC standards
  • Component placement and Mechanical constraints consideration
  • IO and PD routing
  • Design checklist and review consideration
  • Manufacturing and Test files generation
  • Design Documentation
Apply Now

Asst. Manager - Sales Support

Qualification: BE, MBA Equivalent

Experience: 10+ Years

No of Position: 1

Location: Bangalore

Requirements:

  • Manages daily activities of the operational sales support function and sales support team
  • Managing the complete ERP / CRM sales process (customer enquiry, quote, order, execution and completion), backend support and assist the sales team
  • Oversees workflow of all business processing including preparation of reports, charts, and other statistics to support and direct the sales department
  • Manages customer contracts, NDA’s and agreements
  • Assists with budget management to ensure expenses meet target goals.
  • Handle and resolve complex customer requests or complaints in
  • Develops and implements promotional events and interacts with external dealers to increase sales volume.
  • Providing Monthly Sales Info Sheet to Finance with pending info and Tracking
  • Familiar with a variety of the field’s concepts, practices, and procedures
  • Leads and directs the works of other sales team members

Responsibilities:

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Manager / Lead Test Engineer

Qualification: BE/ME in ECE/EEE

Experience: 6 to 10 Years

No of Position: 1

Location: Bangalore

Requirements:

  • Candidate should have minimum 6 to 10 years experience in semi-conductor testing
  • Responsible for working with different teams for understanding the device datasheet and come up with a detailed Test procedure/plan to test the chip in ATE environment
  • Need to interact with the PCB design team for developing the necessary hardware – Test load board, bench board and probe cards
  • Should be responsible for developing the complete ATE test program to validate the chip
  • Should invlove in developing the test methodologies as required

Responsibilities:

  • Work with design/DFT team to develop the detailed test procedure from device data sheet
  • Design and develop the required test hardware- Load board, bench board, Qualification board and probe card
  • Develop the ATE test program for device debug
  • First silicon verification and device bring up using ATE tools and bench equipment
  • Device characterization across temperature, voltage and process corners and validate the chip against the specification
  • Responsible for releasing  the Final production quality test program to the customer (both wafer final test program)
  • Interactions with the Design/DFT team through out the project execution
  • Interact with the customer on a daily basis and provide status update through e-mails and conference calls.
  • Experience in test program release procedure at production test house
  • Responsible from the beginning to the Final test/Wafer Test program release at customer site
Apply Now

Layout Design Engineer

Qualification: BE/ME in ECE/EEE

Experience: 3+ Years

Requirements:

  • Substrate layout design, cadence tools
  • PCB routing,Library creation, RDL routing, simulations
  • Substrate material knowledge is added advantage

Responsibilities:

Apply Now

Junior Design Engineer

Qualification: Engineering / Diploma – ECE/EEE

Experience: 1 Year for Enggineering / 3 years for Diploma holders

Expertise:

  • Substrate layout design, cadence tools
  • PCB routing,Library creation,RDL routing, simulations
  • Substrate material knowledge is added advantage

Responsibilities:

Apply Now

Test Engineer (Post Silicon Validation And Characterization)

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 3 Yrs of exp in Silicon Validation/3 Yrs design exp in Electronics HW

No of Position: 1

Job Description:

  • A candidate with min 3 Years of Experience in Silicon validation and Characterization (OR) min of 3 Yrs design experience in Electronics HW industry with motivation to take up career as Characterization Engineer
  • Strong Electrical engineering fundamentals and exposure on complete HW Development cycle – an added advantage Proven experience in understanding the Device Data Sheet and derive the test methodology based on the Test plan provided Hands-on experience in one or more of the following – highly desirable industry standard Hi-Speed interfaces such as DDR-2, DDR-3, SATA, USB 2.0, USB 3.0, Display Port, PCI-e
  • Proficiency with measurements and related Lab Equipments – is must
  • Exposure on FPGA Design tools such as Xilinx / Altera – a major plus
  • Knowledge on Programming concepts and ‘C’ language – preferred
  • Strong communication skill

Responsibilities:

  • Prepares test and diagnostic programs, designs test fixtures to perform the System Testing & delivery, developing and implementing test automation sequence
  • The job involves device level debug and bring up, co-ordination with team lead to meet the deliverable, Lab Characterization of the Device developed, Device programming/testing new device samples for customers, board debugging etc.
Apply Now

Verification Engineer/Sr.Engineer/Lead

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI

Experience: 3 – 12 years

No of Position: 20

Job Description:

  • 3+ Years of experience on Subsystem/IP verification on multimillion Gate and complex Design with multiple clocks and power domains
  • Testbench and Testplan development
  • Understanding of the design issues in the RTL Experience and working knowledge of HVLs (SV UVM/C/C++), HDLs (Verilog), PLI/DPI, simulators (Questa/VCS) is a MUST
  • Experience in DDRSS, protocols like AHB/AMBA,AXI, ACE and memory controllers
  • Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management

Responsibilities:

Apply Now

RTL SOC Implementation (Senior Level): REQ ID - RTL1

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 – 10 years

No of Position: 1

Job Description:

  • SoC RTL Integration/LEC/Synthesis/Static Timing Analysis.
  • Tools: Synopsys DC Compiler, Primetime/ Signal Integrity.

Responsibilities:

Apply Now

DFT Engineer/Sr.Engineer/Lead

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI

Experience: 3 – 12 years

No of Position: 18

Job Description:

  • Should have sound understanding of all the design for test requirements
  • Should be able to comprehend DFT architecture, architecture limitations, schedule, volume of the task(s)
  • Aware of all the aspects relating to Scan/ATPG
  • Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging
  • Memory bist
  • Test power estimation, Bounday scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing
  • Post-Silicon debug and support
  • Knowledge of test STA
  • Debug skills and Automation savvy
  • Good understanding of Gate-Level simulations and its nuances
  • Translate tool generated patterns to ATE platform
  • Be able to help in silicon debug both on ATE and at system level

Responsibilities:

Apply Now

Physical Design Engineer/Sr.Engineer/Lead

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI

Experience: 3 – 12 years

No of Position: 20

Job Description:

  • Candidate should have 3 to 12 years of complete experience in implementation form Netlist to GDS-II
  • Having hands on Synopsys and Cadence tools is an added advantage
  • Candidate should handle PNR implementation independently for medium complex Hard macros with instance count from 500K to 1M
  • Should handle the timing closure independently for the hard macros
  • Should have worked on PTSI closure
  • Should able to handle FV, CLP, PDN & PV sign off checks for hard macros

Responsibilities:

Apply Now

IP/SoC Logic Design Engineer

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 – 15 years

No of Position: 3

NOTE: This is for ONSITE to US and Valid H1B VISA is Mandatory

Job Description:

  • Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs
  • Participates in the development of Architecture and Microarchitecture specifications for the Logic components
  • Evaluates new feature requests, Designs and develops IP features
  • Provides IP integration support to SoC customers and represents RTL team
  • Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design

Responsibilities:

Apply Now

Analog Designers/Verification/Layout Engineers: REQ ID - ANLG1

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 – 10 years

No of Position: 1

Job Description:

    • Specification study, Verification Plan Development for Analog/Mixed Signal blocks
    • Block Modelling and Verification in Verilog-AMS
    • Chip Top level Functional Simulation
    • Sign-off against Checklist before Tape Out release

Desired Skills & Experience:

  • Prior Analog Verification Experience up to 4 Years
  • Analog Circuit Design knowledge and/or experience
  • Experience in testing of MIPI RF Front End Switches is mandatory.
  • Analog Circuit Design knowledge and/or experience
  • Experience in using Cadence Schematic Editor, ADE in a hands-on manner
  • Mixed Signal Verification
  • Good communication skills
  • Analog Mixed-Signal layout and verification for different complex analog circuits in 45nm node or lesser.Knowledge of half cell Tool Experience like Cadence Virtuso ,Vxl and Virtuoso, Schematic Composer, verifications tools including Assura, Mentor/Synopsys Calibre /Hercules LVS, DRC, STarRC for extraction
Apply Now