Verification & Semiconductors
The premier forum for VLSI design and verification engineers, researchers,
and vendors to discuss challenges, shape practical solutions and define
verification and semiconductor futures.
Date & Time
Tuesday, 23 June 2026
Tuesday, 23 June 2026
9 am – 4.30 pm
Location
University of Reading (UK)
Format
In-person & Online
The Semiconductors Ecosystem –
From Design to Verification
Verification Futures UK 2026, co-located with Semiconductors Futures 2026, delivers a unique blend of
conference presentations, exhibitions, training, and industry networking.
Verification Futures
Formal methods for complex SoCs, CPU & RISC-V verification, open-source tools, AI in DV, verification planning & coverage, and HW/SW co-verification.
Formal Methods
RISC-V
AI in DV
Coverage
Co-Verification
Semiconductors Futures
AI/ML in IP & SoC design, EDA workflows, FPGA, automotive, quantum computing, photonics, and chiplets.
Engineering Students
50+ students with UKESF-supported presentations, mentoring, and career pathways.
Hybrid
Attend in-person at Reading, UK or join online — conference, exhibition, training, and networking.
23 June 2026
University of Reading (UK)
& Online
Advanced EDA Tools & Technologies
Latest Research From Universities
40+ Expert Talks
& Training
Product & Engineering
Experts
10+ Tracks
Event Schedule
Tuesday, 23 June 2026 — Full Day Conference
Special Student Track — UKESF
A dedicated programme for engineering students runs from 11:00 – 16:30, featuring presentations, mentoring, and career pathways.
08:30
Exhibition Opens — Student posters available for viewing
09:25
Conference Starts — Welcome and introductions
09:30
Keynote Address — Ekaterina Almasque — Blank Page Capital
10:00
Platinum Sponsor Presentation — Kartik Hegde — Cadence
10:30
Break — Exhibition & Networking
Parallel
11:00
Latest Verification Methods
Dr. Tobias Ludwig,
LUBIS EDA
Verification Projects using Open Source/License-Free Tools
Ryan Marquess,
Sam Kennedy & Bob Hart ,
Lia Smith, Darwin Chan
University of Southampton
Alpinum RiscV Verification Training
Mike Bartley,
Alpinum Consulting
Parallel
11:30
Latest Verification Methods
Surinder Sood,
ARM
Verification Projects using Open Source / License- Free Tools
Noam Cohen,
Keplertech
Alpinum RiscV Verification Training
Mike Bartley,
Alpinum Consulting
Parallel
11:50
Latest Verification Methods
Sai Karthik Madabhushi,
Synopsys
Verification Projects using Open Source/License-Free Tools
Jerome Sauger,
AXELERA AI
Alpinum RiscV Verification Training
Mike Bartley,
Alpinum Consulting
Parallel
12:10
Latest Verification Methods
Christian Appold,
Denso
Verification Projects using Open Source/License-Free Tools
Doug Carson,
Keysight Technologies
Alpinum RiscV Verification Training
Mike Bartley,
Alpinum Consulting
12:30
Lunch — Exhibition & Networking
Parallel
13:30
Afternoon Verification Session
Darron May,
Siemens EDA
Mixed Signal
Ahmed Mansour,
Alpinum Consulting
Mixed Signal
Mike Bartley,
Alpinum Consulting
Parallel
14:00
Afternoon Verification Session
Matthew Taylor,
Doulos
Mixed Signal
Marcel Ahmedzai,
Cadence Design Systems
Mixed Signal
Mike Bartley,
Alpinum Consulting
Parallel
14:20
Afternoon Verification Session
Kishan Pethani,
AMD
Mixed Signal
Vladimir Zivkovic,
Siemens EDA
Mixed Signal
Mike Bartley,
Alpinum Consulting
Parallel
14:40
Afternoon Verification Session
Neil Dickins,
IC Resources
Mixed Signal
Chris Yates,
Thalia Design Automation
Mixed Signal
Mike Bartley,
Alpinum Consulting
15:00
Break — Exhibition & Networking
Parallel
15:30
Main Afternoon
Abhyarthana Bisoyi,
Odisha University of Technology and Research
AI in DV
Mike Bartley,
Alpinum consulting
Parallel
15:50
Main Afternoon
Katharina Ceesay-Seitz,
ETH Zurich
AI in DV
Shivayogi V Kerudi,
Tessolve
Parallel
16:10
Main Afternoon
Cristian Macario,
MathWorks
AI in DV
Ramesh Krishnamurthy,
APRIL AI Hub Research
16:30
Drinks & Pizza Networking
17:00
Conference Ends
11:00
AI Design IP
Levon Khachatryan,
Voskenai Ltd
11:30
AI Design IP
Alexander Montgomerie-Corcoran,
Heronic Technologies
11:50
AI Design IP
Greg Chadwick,
Fractile
12:10
AI Design IP
James Lewis,
RED Semiconductor International Ltd
12:30
Lunch — Exhibition & Networking
Parallel
13.30
Design
Valentin Peltier,
Secure-IC – A Cadence company
FPGA
Yassine Eben Aimine,
Siemens EDA
Parallel
14:40
Design
John Darlington,
Arm and the University of Southampton
FPGA
Rojalin Mishra,
Riverlane
15:00
Break — Exhibition & Networking
Parallel
15:30
Startups and Breakthrough Technologies
Gaetano De Martino,
Kets Quantum Security Ltd
FPGA
Phill Payne,
Novomorphic
Parallel
15:50
Startups and Breakthrough Technologies
Prof. Rob Young,
Quantum base
FPGA
Simon Southwell,
Wyvern Semiconductors
Parallel
16:10
Startups and Breakthrough Technologies
Kareem Ab,
Synopsys
FPGA
Simon Southwell,
Wyvern Semiconductors
16:30
Drinks & Pizza Networking
17:00
Conference Ends
Speaker Lineup
Industry leaders, researchers, and innovators shaping the future of verification.
Kartik Hegde
Sr Group Director,
Cadence
Dr. Tobias Ludwig
CEO,
LUBIS EDA
Ekaterina Almasque
Co-founder & Managing Partner,
BlankPage Capital
Shivayogi V Kerudi
Asst.Director of Engineering,
Tessolve
Darron May
Director of AI Product Management,
Siemens EDA
Matthew Taylor
Senior Member of Technical Staff,
Doulos
Our Sponsors
Verification Futures 2026 is made possible by the generous support of our
sponsors and exhibitors.
Become a Sponsor
Sponsor packages are available for VF2026 UK. Reach
the verification and semiconductor community —
engineers, researchers, and decision-makers.
