About the Speaker

Sai Karthik Madabhushi is a formal expert based here in the UK with over two decades for formal verification experience. He has worked on multiple tools, designs and with multiple customers over the years. He is currently responsible for multiple facets of product engineering like Usability, GUI, Debug, Signoff and FuSa in the VC Formal team at Synopsys.

Productivity Gains Soar with Formal Advisor

Overview

Synopsys is advancing artificial intelligence across semiconductor design and verification through the Synopsys.ai platform, structured around three pillars: optimization, analytics, and generative AI. AI-driven optimization leverages reinforcement learning and advanced heuristics in tools such as DSO.ai, VSO.ai, TSO.ai, ASO.ai, and 3DSO.ai to improve PPA, accelerate convergence, and reduce design iterations. AI-driven analytics, via Design.da, Fab.da, and Silicon.da, transforms large-scale data into actionable insights for anomaly detection and root-cause analysis. Generative AI enables natural language workflows and automation. This paper explores how these innovations significantly enhance VC Formal productivity and verification efficiency.

Key Points

• Retrieval-Augmented Generation (RAG) is crucial for Formal Advisor Checker Agent to increase property generation accuracy and improve VIP/AIP instantiation productivity
• AI can be leveraged for formal test planning and has shown great promise to improve debugging.
• Helper assertion flow with Formal Advisor has shown exciting potential to help achieve full proofs thus continuing to improve scalability