About the Speaker

Mike Bartley is a semiconductor verification expert with over 35 years of experience spanning software testing, formal methods, and Design Verification (DV). Beginning his career in safety-critical aerospace systems after a PhD in Mathematics, he transitioned into semiconductor verification in 1994 and has since led complex CPU and SoC verification programmes across automotive, mobile, aerospace, and AI domains. Mike has held senior leadership roles at STMicroelectronics, Infineon, Panasonic, ClearSpeed, and Tessolve, where he served as SVP of VLSI. He founded and scaled a global DV services company and now leads Alpinum Consulting, specialising in AI-driven verification, semiconductor engineering, and advanced RISC-V and SoC training programmes.

RISC V Verification Training

Overview

RISC-V is rapidly becoming a foundational architecture for modern CPU and SoC design, driving the need for robust, scalable verification methodologies. This practical, expert-led training equips participants with the skills to verify RISC-V-based CPUs and SoCs using industry-relevant strategies and open-source tooling. Attendees will explore CPU microarchitecture fundamentals, develop structured verification plans, and apply instruction-level testing using riscv-dv, simulators, and custom test generation approaches. The course also covers SoC-level integration, functional coverage closure, debug techniques, and sign-off readiness. By combining theory with hands-on application, participants will gain a clear, practical understanding of end-to-end RISC-V verification in real-world environments.

Key Points

• End-to-end RISC-V verification methodology. The training covers a complete verification flow, from CPU microarchitecture understanding and unit-level verification through to full SoC integration, debug, and sign-off.
• Practical, tool-driven learning approach. Participants gain hands-on experience with instruction stream generation, riscv-dv, simulators, and C/assembly-based test development to validate RISC-V CPUs and SoCs effectively.
• Focus on real-world SoC readiness. The course emphasises functional coverage closure, system-level verification strategies, and debugging techniques to ensure robust, production-ready RISC-V designs.