Verification Futures » VF2025 UK

Verification Futures Conference 2025 UK

The Verification Futures conference has always provided a unique blend of conference presentations, exhibitions, training and industry networking sessions for discussing the challenges faced in hardware and software verification thus providing a unique opportunity for end-users to define their verification challenges and collaborate with the other engineers and vendors to create solutions. In 2025 Verification Futures UK is expanding to include the use of AI/ML in IP/SoC, FPGA and Mixed Signal designs, as well as new tracks for UK Engineering students and UK-based semiconductor start-ups.

Event at a Glance

Tuesday, 01 July 2025 – Full day conference, exhibition and networking event

Reading (UK) & online

FREE to attend conference In-Person or Online

Presentation guidelines for speakers

Conference Program

08:30

Exhibition open and student posters available for viewing

09:25

Conference starts

09:30

The four horse riders of the silicon apocalypse

Sean Redmond (Silicon Catalyst UK)

10:00

Conference Sponsor - Platinum Plus - Cadence

10:30

Break - Exhibition open and student posters available for viewing

	Verification
	Main Morning	Verification Projects using Open Source/License-Free Tools	Training Engineers in work	UKESF	AI Design IP	FPGA Topic #1
11:00	RISC-V Processor Verification Requires the Complete Toolbox Larry Lapides (Synopsys)	AVL – Bringing Industry Best Practise Testbench Design to Open Source Andy Bond (Axelera AI)	Navigating the Verification Maze Matthew Taylor(Doulos)	UK ESF Stream for invited students	Platinum Design IP Sponsor Speaker Speaker TBD	Sponsor speaker(s)
11:30	VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL Anna Duque Antón (RPTU Kaiserslautern-Landau)	Speaker			Rethinking chip(let) design for next generation ADAS applications Martin Zeller(Dreamchip Technologies GmbH)	Designing reusable, portable and secure IP for FPGA designs Steinn Gustafsson(Chevin Technology)
11:50	A novel formal verification solution to Non-convergence Surinder Sood (ARM)	Speaker			Gareth Richard, TechWorks	Speaker
12:10	Speaker	Dynamic CDC Verification: Efficient Approaches for in-house Flows Christian Tchilikov (semify GmbH)			James Red Semiconductor	Speaker

12:30

Lunch - Exhibition open and student posters available for viewing

13:30	Afternoon Verification Session	Mixed Signal	UKESF	Design	FPGA Topic #2 = Verification
13:30	Platinum Verif Sponsor Speaker Siemens – Platinum Sponsor	Platinum Sponsor Speaker	UK ESF Stream for invited students	The Era of Agentic Engineering – Roadmap to Level 5 Bradley Geden (Synopsys)	Platinum FPGA Sponsor Speaker CocoTB
14:00	Bringing CI into Formal Verification Tobias Ludwig (LUBIS EDA)	A Real Number Model of a Phased Array Antenna Daniel Cross, Tim Pylant(Cadence)		Testing and verifying the tools of hardware design John Wickerson(Imperial College London))	CocoTB
14:20	Gold Sponsor Speaker	Digital-Mixed-Signal (DMS) Modelling using Signal Flow Peter Grove(Renesas)		Speaker	HDLRegression: A reliable and efficient tool for FPGA regression testing Marius Elvegård (Inventas)
14:40	Gold Sponsor Speaker	EEnet verification of a Multilevel DCDC converter IC Paul Denny (pSemi)		Speaker	Speaker

15:00

Break - Exhibition open and student posters available for viewing

	Advance Verification Topics
15.30	Main Afternoon	CPU/RISCV Verification (Breakout)	AI in DV	Mixed Signal	UKESF	Breakthrough Technologies	FPGA Topic #3
15:30	Multisim: simulate your RTL with real multi-threaded speed Antoine Madec (Axelera AI)	Configuring Spike to model your RISC-V implementation Mike Thompson (OpenHW Founation)	Kerstin Eder – Bristol University	Beyond Boolean: Smart Abstraction Choices in Mixed-Signal Verification Evgeny Vlasov (Synopsys Inc.)	UK ESF Stream for invited students	Speaker TBD	Speaker
15:50	Speaker TBD	Formal Verification of Security-Properties on RISC-V Processors Christian Appold (Denso Automotive Deutschland GmbH)		Speaker		Speaker TBD	Speaker
16:10	AFCML: Accelerating the Functional Coverage through Machine Learning within a UVM Framework Haroon Waris (Institute of Space Technology (IST))	𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity Katharina Ceesay-Seitz (ETH Zurich)		Steve Holloway Renesas		Speaker TBD	Speaker

16:30

Drinks and Pizza, student poster competition prize giving, sponsor gift raffle draw

17:00

End of conference

Sponsors

VF2025 was made possible through the generosity of the following sponsors. If you would like to become a VF2025 sponsor please Contact Us.