The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.
Event at a Glance
Thursday, 12 September 2024 – Full day conference, exhibition and networking event
Austin Marriott South (USA) and online
FREE to attend conference In-Person or Online
VF2024 Austin Event Programme
Conference Program
| 08:30 | Exhibition open and student posters available for viewing | Slides | Videos |
| 09:25 | Conference starts | ||
| 09:30 | The four horse riders of the silicon apocalypse Conference Keynote – Sean Redmond – Silicon Catalyst UK |
||
| 10:00 |
Dr Andy Penrose (Cadence) |
||
| 10:30 | Break - Exhibition open and student posters available for viewing | ||
| Main Morning AM | |||
| 11:00 | RISC-V Processor Verification Requires the Complete Toolbox Simon Davidmann (Synopsys) |
||
| 11:30 | VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL Johannes Müller(RPTU Kaiserslautern-Landau) |
||
| VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL | |||
| 11:50 | A novel formal verification solution to Non-convergence Surinder Sood (ARM) |
||
| 12:10 | Class-based Design Verification with Python cocotb Matt Bridle (Doulos) |
||
| Multi Track Session AM | |||
| Track 1 :Verification Projects using Open Source/License-Free Tools | |||
| 11:00 | AVL – Bringing Industry Best Practise Testbench Design to Open Source Andy Bond (Axelera AI) |
||
| 11:30 | The DV Digest: Improving the Information Space Brodie Grant(Platform Recruitment) |
||
| 11:50 | Python-based Verification Vs. SystemVerilog-UVM Abdelrahman Mohamed Ali(Si-Vision) |
12:10 | Dynamic CDC Verification: Efficient Approaches for in-house Flows Christian Tchilikov (semify GmbH) |
| Track 2:Training Engineers in work | |||
| 11.00 | Navigating the Verification Maze Matthew Taylor(Doulos) |
||
| Track 3: AI Design IP | |||
| 11:00 | Securing Chiplet-Based AI Designs: Enabling End-to-End Protection in Modular Architectures Brice Gaignoux (Secure - IC / Cadence) |
||
| 11:30 | Testing and verifying the tools of hardware design John Wickerson(Imperial College London)) |
||
| 11:50 | TechWorks-AI and TAIBOM – Engineering Trustable AI Gareth Richards(TechWorks-AI) |
||
| 12:10 | RISC-V: Innovating Within An Established Architecture James Lewis (RED Semiconductor) |
||
| Track 4: FPGA AM | |||
| 11:00 | Impact of EU CRA and Cyber Regulations on FPGA Ian Pearson(Microchip Ltd.) |
||
| 11:30 | Designing reusable, portable and secure IP for FPGA designs Steinn Gustafsson(Chevin Technology) |
||
| 11:50 | Unlock Silicon Flexibility: Design for the Future with Programmable Platforms Owen Bateman (QuickLogic) |
||
| 12:10 | Bio-inspired CODECs using steganography Dr Pedro Machado (Nottingham Trent University) |
||
| 12:30 – 13:30 | Lunch | ||
| Main Afternoon PM | |||
| 13:30 | Synergistic stimulus-free verification with next generation static and formal Yassine Eben Aimine (Siemens EDA) |
||
| 14:00 | Bringing CI into Formal Verification Tobias Ludwig (LUBIS EDA) |
||
| 14:20 | Advanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC David Kelf(Breker Verification Systems) |
||
| 14:40 | How Will AI Change Your Verification Future? Neil Dickins (IC Resources) |
||
| 15:30 | Multisim: simulate your RTL with real multi-threaded speed Antoine Madec (Axelera AI) |
||
| 15:50 | Unify to Verify: A Monorepo Approach for Hardware and Software using Bazel, Cocotb and Verilator Will Keen(Fractile Ltd) |
||
| 16:10 | A Novel Security Vulnerability Detection Mechanism Using Information Flow Tracking on a given SOC Surinder Sood(ARM) |
||
| Multi Track Session PM | |||
| Track 1 :Mixed Signal | |||
| 13:30 | A Real Number Model of a Phased Array Antenna Daniel Cross, Tim Pylant(Cadence) |
||
| 14:20 | Digital-Mixed-Signal (DMS) Modelling using Signal Flow Peter Grove(Renesas) |
||
| 14:40 | EEnet verification of a Multilevel DCDC converter IC Paul Denny (pSemi) |
||
| 15:30 | Beyond Boolean: Smart Abstraction Choices in Mixed-Signal Verification Evgeny Vlasov (Synopsys Inc.) |
||
| 16:10 | UVM-MS: A Concrete Example using a DAC Steve Holloway (Renesas) |
||
| Track 2: Design | |||
| 13:30 | Priyankari Chevuturi (Synopsys) The Era of Agentic Engineering – Roadmap to Level 5 |
||
| 14:00 | Rethinking chip(let) design for next generation ADAS applications Martin Zeller(Dreamchip Technologies GmbH) |
||
| 14:20 | Pre-silicon Identification of Security Vulnerabilities Doug Carson (Keysight Technologies) |
||
| 14:40 | Rethinking AI Inference through Differentiable Logic Gate Networks (difflogic) Georg Meinhardt (DiffLogic Inc. ) |
||
| Track 3: FPGA PM | |||
| 13:30 | Use of Prototyping and Emulation in the semiconductor industry in 2025 Michael O’Sullivan (Cadence Design Systems) |
||
| 14:00 | Automating the design of bespoke AI accelerators for FPGAs Alexander Montgomerie-Corcoran(Heronic Technologies) |
||
| 14:20 | HDLRegression: A reliable and efficient tool for FPGA regression testing Marius Elvegård (Inventas) |
||
| 14:40 |
Yassine Eben Aimine (Siemens EDA) |
||
| 15:00 | Refreshments Break | ||
| Track 4: CPU/RISCV Verification | |||
| 15:30 | Automating Cyber-physical Security Verification in the SoC Design Flow Valentin Peltier (Secure- IC /Cadence) |
||
| 15:50 | Formal Verification of Security-Properties on RISC-V Processors Christian Appold (Denso Automotive Deutschland GmbH) |
||
| 16:10 | 𝜇CFI: Formal Verification of Microarchitectural Control-flow Integrity Katharina Ceesay-Seitz (ETH Zurich) |
||
| Track 5: AI in DV | |||
| 15:30 | Efficiency Improvement and Automation in Design Verification using AI Marmik Soni (Tessolve Semiconductor Pvt Ltd) |
||
| 15:50 | Case Study on deploying AI in Design Verification for Smarter and Faster Verification of Designs Arjumand Yaqoob(Qualcomm Incorporated) |
||
| 16:10 | Validate and Implement a RISC-V core using AI Vidushi Yaksh, William Ly (University of Southampton) |
||
| Track 6: Breakthrough Technologies | |||
| 15:30 | Splitting the die: a modular approach to chiplet design and verification Mark Knight (Arm) |
||
| 15:50- | TrIM: An Efficient Systolic Array for Convolutional Neural Networks Dr Cristian Sestito (AI Hub for Productive Research & Innovation in eLectronics (APRIL), The University of Edinburgh, UK) |
||
| 16:10 |
Kauser Johar (Chipletti) |
||
| Track 7: FPGA Training | |||
| 15:30 | Improving your VHDL FPGA verification with OSVVM and UVVM Matt Bridle(Doulos) |
||
| 16:30 | Drinks and Pizza, student poster competition prize giving, sponsor gift raffle draw | ||
| 17:00 | End of conference |
Sponsors
VF2024 was made possible through the generosity of the following sponsors. If you would like to become a VF2024 sponsor please Contact Us.
