The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.
Event at a Glance
Tuesday, 18 June 2024 – Full day conference, exhibition and networking event
Reading (UK) & online
FREE to attend conference In-Person or Online
Conference Program
| 08:30 | Arrival: Breakfast and Networking | Slides | Videos |
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||
| Keynote Speakers | |||
| 09:30 | The Ghosts of Challenges Past, Present and Future Andy Bond (Axelera AI) |
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| 10:05 | Mobilise your data to drive predictable verification Bryan Dickman, Joe Convey (Silicon Insights Limited) |
10:20 | Challenges of Developing Silicon for Automotive Darren Galpin |
| 10:30 | AI and GenAI for Verification Productivity Dr Andy Penrose(Cadence) |
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| 11:00 | Skills. Twelve Months on from Semiconductor Strategy, is there Progress? Stewart Edmondson(UK Electronics Skills Foundation) | ||
| 11:05 | Refreshments and Networking | ||
| Multi-Track Session (AM) | |||
| User presentations on Formal Verification | |||
| 11:30 | Taming formal with intelligent automation? Tobias Ludwig (LUBIS EDA) |
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| 11:50 | End to End Formal Verification of Processors with Fine-Grained Memory Protection Professor Tom Melham (University of Oxford) |
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| 12:10 | A Semi-formal approach to coverage analysis and System-on-Chip debugging Dr. Surinder Sood(ARM) |
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| Track 2 - Training Session 1 | |||
| 11:30 | Introduction to Verification and SystemVerilog for Beginners Matthew Taylor (Doulos) |
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| Track 3 - VHDL Verification- TBC | |||
| 11:30 | Essential Steps to Simplify VHDL Testbenches Using OSVVM Jim Lewis (SynthWorks Design Inc) |
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| 12:30 | Lunch and Networking | ||
| 13:30 | Autonomous Verification – Are We There Yet? Bradley Geden (Synopsys) |
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| 14:00 | RISC-V Verification: New Techniques and Approaches for SoC Validation Adnan Hamid (Breker Verification Systems) |
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| 14:20 | Finishing coverage closure in a controlled way Rainer Ulrich, Saurav Kumar (Advanced Micro Devices) |
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| 14:40 | Introducing Smart Verification: Unleashing the Potential of AI within Functional Verification Gabriel Chidolue, Siemens Digital Industries Software |
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| 15:00 | Refreshments and Networking | ||
| Multi-Track Session (PM) | |||
| Track 1 - Latest topics in Verification | |||
| 15:30 | Challenges and opportunities in SystemC and HLS based functional verification Sreejith Sudhakaran(Qualcomm Technologies International, Ltd. ) |
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| 15:50 | Extending riscv-dv to suit your specific needs. Mike Thompson (OpenHW Group) |
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| 16:10 | Presentation title speaker name and company name |
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| Track 2 - Training Session 2 | |||
| 15:30 | Is it easy to get started with UVM, or should I use Formal instead? Matthew Taylor(Doulos) |
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| Track 4 - UVM for MS Verification | |||
| 15:30 | Generic Monitor for Mixed Signal Designs Peter Grove (Renesas) Randomisation in the Real world Steven Holloway (Renesas) |
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| 16:30 | Event Closes |
Sponsors
VF2024 was made possible through the generosity of the following sponsors. If you would like to become a VF2024 sponsor please Contact Us.
