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Finishing coverage closure in a controlled way

Conference: Verification Futures 2024 (click here to see full programme)
Speaker: Rainer Ulrich, Saurav Kumar
Presentation Title: Finishing coverage closure in a controlled way

Closing the last remaining coverage holes to achieve 100% coverage is very time-consuming: We are proposing a scheme to triage the remaining holes to allow a better risk assessment for project management and to decide how to prioritize the work. Coverage merge between different EDA tools can help close coverage goals faster in scenarios where different teams and IP hierarchies are using varied tools for verification and/or emulation. Given the lack of a common support across EDA tools this presentation summarizes adopted ways to merge coverage and the types of issues encountered during this process.

Speaker Bio:

Rainer has more than 30 years experience working on ASIC/SOC design in both start-ups and blue chip companies including Broadcom and Siemens. The last 10 years he has focused on verification. He works currently in AMD’s Video Core team as verification lead ensuring together with peers across multiple groups that the latest techniques and technologies are included in the flow to speed up and improve the quality of verification.

Saurav has worked on pre-silicon verification of ASIC/SoC in domains like imaging, factory automation and IoT for last 18 years at various companies. At AMD Cambridge, he is working in Data Centre Group to verify ASIC design targeted for low-latency networking and AI training applications. He has an aptitude for improving the quality of verification and time to market and consistently strives to find areas which can be automated.

Key Points:
  • Meaningful coverage closure requires identifying the impact of the holes
  • Proposed metric allows a better risk assessment
  • Use of multi-vendor tools can speed up coverage closure
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