Finishing coverage closure in a controlled way

Conference:	Verification Futures 2024 (click here to see full programme)
Speaker:	Rainer Ulrich, Saurav Kumar
Presentation Title:	Finishing coverage closure in a controlled way
Abstract:	Closing the last remaining coverage holes to achieve 100% coverage is very time-consuming: We are proposing a scheme to triage the remaining holes to allow a better risk assessment for project management and to decide how to prioritize the work. Coverage merge between different EDA tools can help close coverage goals faster in scenarios where different teams and IP hierarchies are using varied tools for verification and/or emulation. Given the lack of a common support across EDA tools this presentation summarizes adopted ways to merge coverage and the types of issues encountered during this process.
Speaker Bio:	Rainer has more than 30 years experience working on ASIC/SOC design in both start-ups and blue chip companies including Broadcom and Siemens. The last 10 years he has focused on verification. He works currently in AMD’s Video Core team as verification lead ensuring together with peers across multiple groups that the latest techniques and technologies are included in the flow to speed up and improve the quality of verification. Saurav has worked on pre-silicon verification of ASIC/SoC in domains like imaging, factory automation and IoT for last 18 years at various companies. At AMD Cambridge, he is working in Data Centre Group to verify ASIC design targeted for low-latency networking and AI training applications. He has an aptitude for improving the quality of verification and time to market and consistently strives to find areas which can be automated.
Key Points:	Meaningful coverage closure requires identifying the impact of the holes Proposed metric allows a better risk assessment Use of multi-vendor tools can speed up coverage closure

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

AI chips must get the math right

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification

3 Key Points:

Floating-point unit (FPU) for AI chips

FPU Formal Verification App

Compliance with IEEE-754

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

Finishing coverage closure in a controlled way

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ML Verification Turns Convention on its Head

An Emulation Strategy for Artificial Intelligence Designs

AI chips must get the math right

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