Generic Monitor for Mixed Signal Designs

Having a UVM (or not) environment where you can monitor a node irrespective of the datatype simplifies the ability to switch the abstraction of the DUT without changing the environment. Components that are agnostic enable simulations to run or debugged using RNM before running longer and more expensive AMS/Schematics. The monitor must be in a module and this presentation will show how a DUT abstraction agnostic monitor can be created that can be controlled. The example assumes the node in question is steady state, but more elaborate signal trackers could be created.

Peter has worked in the industry starting back in 2001 when he joined a small company called Wolfson MicroElectronics, where he was project lead for more than 15 production devices. Since then Peter has only worked at one other company, Nujira, before joining Dialog (now Renesas) at their Edinburgh office. Peter has been with Dialog since 2014. Peter’s background has been main digital design, but has over the years taken charge of many large mixed signal devices that are in volume production and been exposed to enough analogue design work to appreciate the issues they face in verification. Peter has an eye for looking for ways in which techniques can be done to improve chip level coverage, simulation runtime improvement to name a few.

Peter is also in a unique position that during his days at Wolfson he was a key player in defining their schematic/Layout tool set with integrated revision control. This has allowed Peter to gather a large number of skills not just in design work but in all the backend flows and EDA tools, understanding different netlist types and how the tools work.

Peter’s technical interests are mixed signal and analogue verification methodologies, design flows. Peter also is an Acellera SystemVerilog-AMS committee chair, UVM-AMS member/key contributor making sure the ‘users’ feedback on the language is considered and not what the vendors just want to support.