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A Semi-formal approach to coverage analysis and System-on-Chip debugging

Conference: Verification Futures 2024 (click here to see full programme)
Speaker: Dr. Surinder Sood
Presentation Title: A Semi-formal approach to coverage analysis and System-on-Chip debugging

The most challenging task in the System on Chip (SoC) development cycle is design validation and assurance that validation covers the entire design exhaustively, which is ensured using various coverage metrics. Due to tricky system level corner case scenarios, SoC coverage holes are observed. This coverage hole analysis can be done via multiple approaches. The most often used approaches are the tracker-based approach and the Waveform Dump (WD)-based approach. The issue with the tracker-based approach is that the trackers are not timing accurate and not always reliant due to many approximations in their generation flow.

Another approach is to debug and analyze using WD manually. WD with integrated tools like waveform debugger is extensively used for this purpose. The compute resources and time taken to launch signal dumps and debug the waveform are massive at the SoC-level and also lead to huge compute resources or lag in many cases. The lag time specifically, is of the order of hundreds of minutes in many cases. Consequently, SoC debug, micro-architectural analysis, and post-simulation analysis involves a lot of time and effort. We address this problem by developing an offline semi-formal approach that uses a temporal logic-based query mechanism.

This mechanism provides us to write system-level contracts which are decomposed of component-level guarantees. These are defined using Linear Temporal Logic (LTL) properties (called queries in this case) to Timed LTL and help realize an offline property justification framework. The proposed framework helps debug the failure using timed LTL queries on the WD and results are returned within a few seconds, consequently, making debugging easy. Moreover, this solution comes with a package of many allied benefits, which are described in the paper. We claim to improve the debug effort as we get a speedup of the order of 4x while debugging failed scenarios, as well as a significant improvement in coverage analysis.

Speaker Bio:

Surinder sood holds Phd in design verification and validation of hybrid systems from The University of Auckland, New Zealand. He has an overall experience of 20 years. Most of the time he has spent in verification of hardware components to system on chips. He has worked on different verification techniques while verifying such designs. His research interests include formal verification of digital and hybrid systems. He has also done work in security vulnerability verification of digital hardware, and also performance estimation of SOCs while doing SOC verification. He has worked with many prestigious organizations like Intel, AMD, Samsung electronics, ST Microelectronics and SanDisk. Currently he is working for ARM as a principal engineer and is a Senior member of IEEE-Circuit and Systems Society.

Key Points:
  • Linear Temporal logic
  • Formal verification
  • System on Chips
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