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UVVM: UVM for VHDL designers – An introduction

Conference: DVCLUB Europe | UVVM
Speaker: Espen Tallaksen, EmLogic
Speaker Title: UVVM: UVM for VHDL designers – An introduction
Abstract: UVVM (Universal VHDL Verification Methodology) is the world-wide #1 VHDL Verification methodology and library. This is due to the improvement UVVM yields in both FPGA quality and development time. This open source Library and Methodology has the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner providing modularity, reusability, constrained-random stimulus and functional coverage similar to UVM. UVVM also has the largest library of open source VHDL verification models and components. With more than 50% of all FPGA designers using VHDL, UVVM provides a great verification solution for these users. This presentation will provide an introduction to UVVM and get you started using UVVM on your next (or current) project.

Key Points:

  • Efficient verification for high quality and unique reuse
  • Simple testbenches and a basic infrastructure for simple DUTs
  • Efficient Bus Functional Modules
  • Verification components and their advantages
  • Constrained Random and Functional Coverage
  • Advanced testbenches with transactions, models and scoreboards
Speaker Biography: Espen Tallaksen is the CEO of EmLogic, in Norway.
Espen is also the author and architect of UVVM, the leading verification methodology and library for VHDL.
He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given lots of presentations at various international conferences with great feedback. He is also giving courses on FPGA Design and Verification.


DVCLUB Europe is made possible through the generosity of our sponsors.

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