VLSI Design,

Enters The Next Level

Design Engineering

Rich experience, innovative mindset – driving Chip solutions

Since inception in 2012, increasing demand has ushered significant growth for Tessolve’s VLSI capabilities. The team too has flourished with expertise and capability in multiple domains. Today, we are poised to be the leading chip solutions provider across verticals – Automotive, Server, Graphics and mobile platforms, to name a few. Our design team works cohesively with client’s Embedded, Test, PCB and Validation teams to provide relevant, rewarding and complete solutions.

The Process/Technology Nodes:

  • Design Solutions from Specifications to GDS sign-off, across process nodes from 350nm to most advanced 7nm
  • Domain experience includes Data Converters, Power Management, High Speed Interfaces – PCIe, DDR, SerDes, SAS/SATA, Ethernet, MIPI, Foundation IPs etc.
  • Experience in Pre-silicon verification, FPGA prototyping and Emulation
  • Expertise in Post-silicon validation on Bench Char and ATE
  • DFT and DFD expertise involves test and debug specific microarchitecture, RTL and DV, pattern generation and post silicon bring-ups
  • Expertise in low power with the knowledge and experience in power savings and management techniques

Our IC Capability Circuitry

DFT to Analog, we chip into all with dedication

Design Verification

Design For Test & Debug

Physical Design

FPGA Emulation & Validation

Analog & Mixed Signal

Design Verification

Silicon success thanks to design prowess

Design Verification (DV) clicks when the right methodology is complemented by the right team. First tie silicon success isn’t easy but that’s what our DV engineers bring to you. Extensive knowledge, experience enables them to comprehend the tasks and execute flawlessly.
Kick-starting with feature extraction, properties DV project ends with sign-off checklist covering functional aspects, codes, performance, and power. System modeling is leveraged in HW/SW co-verification with our verification architects expertly handling optimal trade-offs.

DV – The Highlights:

  • Languages and Methodologies: C/C++/SystemVerilog/Verilog/SystemC/UVM
  • Protocol Knowledge: PCIe, DDR, SATA/SAS, Ethernet
  • Processor Expertise: ARM, MIPS
  • Low Power Verification – UPF Power-aware RTL and Gate Simulation
  • Formal/Static Property based Verification
  • Emulation Platforms – Zebu, Palladium, Veloce
  • Post silicon validation

Design For Test And Debug

Engineering chip anatomy with testability and debugging

Design For Testing (DFT) and Debugging (DFD) are critical stages in the micro-architectural phase of the design. Working in tandem with client’s design team, our experts understand the anatomy of the chip and thus helps carve out its DFT and DFD architecture. They leverage the implemented DFT architecture incorporating RTL and design verification via the pattern generation phase.


DFT & DFD – The Highlights:

Complex design samples we handled including, but not limited to

  • Multiple Clock and Voltage Domains
  • Mixed signal low speed and high speed designs
  • Power sensitive designs
  • Embedded processor based designs
  • Large number of memory types – SRAM, ROM, CAM etc.
  • Complex analog testing includes SERDES, DDR and A/D, D/A converters
  • Experience in industry standard EDA tools for Memory BIST, ATPG, JTAG etc. from Mentor Graphics, Synopsys and Cadence
  • Post silicon debug on ATE and Bench, demonstrating ownership from silicon architecture through silicon production

Physical Design

Motivated team, better design capability

Rich and extensive Physical Design (PD) experience has enabled the team to work on multiple successful tape-outs. Fully versed in Industry standard EDA tools and well trained to handle low power, high performance and area critical designs, the VLSI Physical Design team at Tessolve leads the design excellence.

PD – The Highlights:

  • Experience in industry leading 7nm nodes.
  • Experience in PDKs from industry leading fabs
  • Mixed signal designs
  • Low Power designs
  • High Performance designs
  • EDA tool experiences include most industry leading tools from Synopsys, Mentor, Cadence, Ansys etc.
  • Closed timing in multiple process corners as per the application requirements Server, Graphics, Mobile, Audio, Networking, Automotive

FPGA Emulation and Post SI Validation

Prototyping across multi platforms – we make it possible

A full-service spectrum covering FPGA Design, FPGA Prototyping and Emulation Flows. Pre-Silicon Validation, SW development is done leveraging FPGA Prototyping platforms. Emulations, on the other hand, is used for HW/SW verification and full system validation.

FPGA Emulation – The Highlights:

Complex design samples we handled including, but not limited to

  • Tools expertise – Synthesis (Synolify Premier/Pro, Altera Tools), PAR & Timing Analysis (Xilinx & Altera Tools), Debug (Chip scope Altera Signal, Logic Analyzer, Oscilloscope, Trace 32)
  • Simulation Tools – Modelsim, NCSIM, Questasim

Analog & Mixed Signal (AMS) Design

Agile and high quality – analog design creation

Analog and Mixed signal design team at Tessolve specializes in High quality design for different applications with process nodes varying from 350nm to most advanced 7nm designs. The IPs were developed for different industry verticals like Automotive, Communication, Consumer, Medical, IoT etc. The competent team has rich experience of successfully delivering more than 50+ silicon proven analog chips during last few years with full ownership of the delivery from Spec to GDSII sign off, supported with silicon validation to global semiconductor companies.

Analog & Mixed Signal – The Highlights:

  • Hands-on complete analog life-cycle from specs till post-silicon validation
  • Expertise on SoC & block level
  • Expertise on CMOS/FinFET process node: 10nm, 14nm, 22nm, 45nm, 65nm, 90nm, 130nm, 180nm & 350nm
  • High Speed AMS Design & Layout
  • RF Layout
  • IO Design & Layout
  • Standard Cell Design & Layout
  • Verilog, Verilog-A & VAMS modeling