VLSI Design

Enters The Next Level

Design Engineering

Rich experience, innovative mindset – driving Chip solutions

Complementing Tessolve’s post silicon Test engineering solutions, VLSI design capabilities are added to our service portfolio in 2012. This is to support the increasing demand for design solutions for the state-of-the-art VLSI chipsets. The team was built with expertise and capability in multiple domains and technologies. Today, we are poised to be the leading solutions provider for Chip Designs across verticals – Automotive, Server, Graphics and mobile platforms, to name a few. Our design team works cohesively with Embedded, Test, PCB and Validation teams to provide relevant, rewarding, and complete solutions.

The Process/Technology Nodes:

  • Design Solutions from Specifications to GDSII sign-off for Analog, Digital and Mixed Signal chips, across process nodes from 350nm to most advanced 5nm
  • Digital Design Turnkey Capabilities – RTL, DV, DFT, PD, till GDS sign off
  • Analog/AMS Design Turnkey Capabilities – Analog Modelling, Circuit Design, Layout Design, AMS Verification
  • Domain experience includes Data Converters, Power Management, High Speed Interfaces – PCIe, DDR, SerDes, SAS/SATA, Ethernet, MIPI, Foundation IPs etc
  • Applications include Servers, Automotive, Graphics, Mobile platforms, Medical, Consumer products etc
  • Expertise in Pre-silicon verification, FPGA Prototyping and Emulation
  • Expertise in Post-silicon validation on Bench Char and ATE
  • Expertise in Low power, High Power, High Speed designs with the knowledge and experience in power savings and design optimisation techniques

Our IC Capability Circuitry

DFT to Analog, we chip into all with dedication

Analog & Mixed Signal

RTL Design

SystemC Solutions

Design Verification (DV)

Design for Test (DFT)

Physical Design

FPGA Emulation & Validation

Analog & Mixed Signal (AMS) Design

Agile and high quality – analog design creation

Analog and Mixed signal design team at Tessolve specializes in High quality design for different applications with process nodes varying from 350nm to most advanced 5nm designs. The IPs were developed for different industry verticals like Automotive, Communication, Consumer, Medical, IoT etc. The competent team has rich experience of successfully delivering more than 50+ silicon proven Analog chips during last few years with full ownership of the delivery from Spec to GDSII sign off, supported with silicon validation to global semiconductor companies.

Analog & Mixed Signal – The Highlights:

  • Complete Analog Design life-cycle from specs to post-silicon validation
  • Expertise for developing Full IP & Block level
  • Expertise on CMOS/FinFET process node: 5nm, 7nm, 10nm, 14nm, 22nm, 45nm, 65nm, 90nm, 130nm, 180nm & 350nm
  • High Speed AMS Design & Layout
  • RF Layout
  • IO Design & Layout
  • Standard Cell Design & Layout
  • Verilog-A & V-AMS Modelling

RTL Design

Tessolve offers RTL design from product specification which include Synthesis & Post Netlist simulations. And supports integration of RTL Blocks for full SOC development.


Highlights:

  • Integration: Block integration, Clocks and Reset, Clock gating, DFT and DFD, Lint, CDC
  • IP Block Development: Reusable, Pipelined, CDC, Lint, DFT, HW-SW partitioning
  • Protocols: AMBA CHI/AXI/AHB/APB, MIPI (DSI, CSI, Slimbus, Soundwire, Unipro, NAND Flash); PCIe; SAS/SATA; SDIO Host/Device/Memory/Combo; I2C, SPI, UART, MDIO

SystemC Solutions

SystemC addresses the need for a system design and verification language that spans hardware and software. It is a language built in standard C++ by extending the language with a set of class libraries created for design and verification. Tessolve customers are applying SystemC for architectural exploration, performance modelling, functional verification, and high-level synthesis.

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Design Verification

Silicon success thanks to design prowess

Hardware Verification is the process of checking the design functionality for the given specifications. It is one of the largest tasks in silicon development and has the biggest impact on the key business drivers of quality, schedule, and cost. Tessolve offering covers all aspects of Verification flow from feature extraction to coverage closure and equipped with custom-designed verification productivity tools for reducing verification turnaround times. Tessolve bring verification expertise across multiple industry verticals spanning Consumer Electronics, Wireless, Data Centre, Automotive and Memory/Storage segments.

DV – The Highlights:

  • Flexible resources proficient in verification methodologies and tools.
  • Tools for verification productivity
  • Consultancy programs and continuous improvements through Benchmarking.
  • Training on verification strategy and the latest verification methodologies.

Key expertise areas

  • Languages and Methodologies: C/C++/SystemVerilog/Verilog/SystemC/UVM
  • Protocol Knowledge: High-speed, ARM-based, Memory, Storage, Serial IO, MIPI
  • Processor Expertise: ARM, MIPS, x86, Power
  • Low Power Verification – UPF Power-aware RTL and Gate Simulation
  • Formal/Static Property based Verification
  • Emulation Platforms – Zebu, Palladium, Veloce
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RISC-V Test and Verification Solutions

Design For Test And Debug

Engineering chip anatomy with testability and debugging

Design For Testing (DFT) and Debugging (DFD) are critical stages in the micro-architectural phase of the design. Working in tandem with client’s design team, our experts understand the anatomy of the chip and thus helps carve out its DFT and DFD architecture. They leverage the implemented DFT architecture incorporating RTL and design verification via the pattern generation phase.


DFT & DFD – The Highlights:

Complex design samples we handled including, but not limited to

  • Multiple Clock and Voltage Domains
  • Mixed signal low speed and high-speed designs
  • Power sensitive designs
  • Embedded processor-based designs
  • Large number of memory types – SRAM, ROM, CAM etc.
  • Complex Analog testing includes SERDES, DDR and A/D, D/A converters
  • Experience in industry standard EDA tools for Memory BIST, ATPG, JTAG etc. from Mentor Graphics, Synopsys and Cadence
  • Post silicon debug on ATE and Bench, demonstrating ownership from silicon architecture through silicon production
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Physical Design

Motivated team, better design capability

Rich and extensive Physical Design (PD) experience has enabled the team to work on multiple successful tape-outs. Expertise with all Industry standard EDA tools, Design Flow and well trained to handle low power, high performance area critical designs.

PD – The Highlights:

  • Experience in most advanced Process nodes down to 5nm.
  • Integration of Analog & Mixed signal SOC
  • Low Power design
  • High Performance design
  • Expertise on all industry standard EDA tools – Synopsys, Mentor, Cadence, Ansys etc.

FPGA Emulation and Post SI Validation

Prototyping across multi platforms – we make it possible

The team has extensive experience in successfully executing FPGA programs for customers across Networking, Automotive, Industrial and Consumer Electronics domains. The team has delivered 80 + FPGA products with multiple specs involving bit-file generation and validation programs. Expertise areas include high Speed Interconnects, Bus Interfaces, Network Protocols, SoC Interfaces, Audio/Video Applications and Controllers.

We offer full-service spectrum covering FPGA Design, FPGA Prototyping and Emulation Flows. Pre-Silicon Validation, SW development across different platforms.

FPGA Emulation – The Highlights:

Complex design samples we handled including, but not limited to

  • Tools expertise – Synthesis (Synolify Premier/Pro, Altera Tools), PAR & Timing Analysis (Xilinx & Altera Tools), Debug (Chip scope Altera Signal, Logic Analyzer, Oscilloscope, Trace 32)
  • Simulation Tools – Modelsim, NCSIM, Questasim