The Verification Futures conference has always provided a unique blend of conference presentations, exhibitions, training, and industry networking sessions to discuss the challenges faced in hardware verification. It is a unique opportunity for end-users to define their verification challenges and collaborate with engineers and vendors to create solutions. In 2025, Verification Futures US will also reflect the growing use of AI/ML in IP/SoC designs and verification, with an increased number of talks on these key topics.
Event at a Glance
Wednesday, 12 November 2025 – Full day conference, exhibition and networking event
Austin Marriott South (USA) and online
FREE to attend conference In-Person or Online
Conference Program
| 08:30 | Arrival: Breakfast and Networking | Verifying Heterogeneous Systems||
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||
| 09:30 | Si Catalyst - Keynote Speaker | ||
| 10:15 | Speaker TBD –Challenge Paper |
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| 10:30 | Speaker TBD |
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| 11:00 | Refreshments and Networking |
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| 11:30 | Verifying Heterogeneous Systems |
Doulos | Continuing Progress in Verification: A Mixed Signal Approach |
| 11:30 | Static Sign-Off Methodologies: Liberating Functional Verification from Boolean Shackles Prakash Narain - Real Intent |
Overcoming Obstacles to Model-based Verification Daniel Cross - Cadence Design Systems |
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| 11.50 | Property Generator: simple generation of Formal Assertion IP Dr. Tobias Ludwig - LUBIS EDA |
Modelling a 4-Level DCDC Converter Using EEnets Abhijit Madhu Kumar - Cadence Design Systems |
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| 12:10 | Speaker TBD |
Practical Approaches to Adopting State of the Art Mixed Signal Solutions Umar Lyles - Cirrus Logic |
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| 12:30 | Lunch and Networking |
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| 13:30 | Improving verification to Accelerate Shift-Left |
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| 13:30 | Speaker TBD |
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| 14:00 | Speaker TBD |
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| 14:20 | Speaker TBD |
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| 14:40 | Speaker TBD |
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| 15:00 | Refreshments and Networking |
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| 15:30 | Real Examples of Applying GenAI and Formal Verification |
Doulos | TBD |
| 15:30 | Chandrashekar Punajoor Lokeshappa - Tessolve |
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| 15:50 | Applying Generative AI in Post-Silicon Validation: Real Use Cases and Technical Insights Santosh Appachu Devanira Poovaiah - NVIDIA Corporation |
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| 16:10 | Deploying AI in DV for smarter and faster IP verification Arjumand Yaqoob - Qualcomm Incorporated |
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| 16:30 | Event Closes | ||
Sponsors
VF2025 was made possible through the generosity of the following sponsors. If you would like to become a VF2025 sponsor please Contact Us.
