The Verification Futures conference has always provided a unique blend of Conference presentations, exhibitions, training, and industry networking sessions to discuss the challenges faced in hardware verification. It is a unique opportunity for end-users to define their verification challenges and collaborate with engineers and vendors to create solutions. In 2025, Verification Futures US will also reflect the growing use of AI/ML in IP/SoC designs and verification, with an increased number of talks on these key topics.
Event at a Glance
Wednesday, 12 November 2025 – Full day conference, exhibition and networking event
Austin Marriott South (USA) and online
FREE to attend conference In-Person or Online
VF2025 Austin Event Programme
Conference Program
| 08:30 | Arrival: Breakfast and Networking | Slides | Recordings |
| 09:25 | Welcome: Mike Bartley - Alpinum Consulting | ||
| 09:30 | Revitalizing Semiconductor Startups Keynote - Tarun Verma - Silicon Catalyst |
Download | Recording not available |
10:15 | Overcoming the Challenges of Blending Hardware Verification Expertise with AI and Machine Learning Keynote Challenge Paper - Sohil Sri Mani Yeshwanth Grandhi - NVIDIA Corporation |
Download | View |
| 10:30 |
Wei-Hua Han - Synopsys |
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| 11:00 | Refreshments and Networking | ||
| Verifying Heterogeneous Systems | |||
| 11:30 | Static Sign-Off Methodologies: Liberating Functional Verification from Boolean Shackles Prakash Narain - Real Intent |
Download | Recording not available |
| 11.50 | Property Generator: simple generation of Formal Assertion IP Dr. Tobias Ludwig - LUBIS EDA |
Download | View |
| 12:10 | Harnessing Agentic AI to Accelerate Verification Chuck Alpert - Cadence |
Download | View |
| Doulos Know How Tutorial: Beginner’s Guide to Using AI for Hardware Engineering | |||
| 11:30 | Beginner’s Guide to Using AI for Hardware Engineering Doug Smith - Doulos |
Download | View |
| Emerging Hardware Technologies and Startups | |||
| 11:30–11:40 |
Tarun Verma - Silicon Catalyst |
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| 11:40–12:00 | Emerging Trends in AI for Chip Design and EDA David Z. Pan - The University of Texas at Austin |
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| 12:00–12:15 | Ultra-fast AI Inference at the Edge Frank Thiel - Gigantor Technologies |
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| 12:15–12:30 | New sensing technologies providing insight inside batteries Rick Seger - SigmaSense |
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| 12:30 | Lunch and Networking | ||
| 13:30 | Improving verification to Accelerate Shift-Left | ||
| 13:30 | Bridging the Gap: A Practical Roadmap to Formal Verification for DV Engineers Vivek Raheja, Harsh Vardhan Gupta, Gilberto Migliorin - Synopsys |
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| 14:00 |
Jeffrey Pan - Bronco AI, Inc. |
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| 14:20 | Improving verification to Accelerate Shift-Left Sheela Pillai |
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| 14:40 | The Intelligent Verification: Reinventing 5 DV Workflows with AI Shelly Henry - Moores Lab AI |
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| 15:00 | Refreshments and Networking | ||
| 15:30 | Real Examples of Applying GenAI and Formal Verification | ||
| 15:30 |
Georg Meinhardt - DiffLogic Inc. |
Speaker Slides not available |
Recording not available |
| 15:50 | Applying Generative AI in Post-Silicon Validation: Real Use Cases and Technical Insights Santosh Appachu Devanira Poovaiah - NVIDIA Corporation |
Download | Recording not available |
| 16:10 | Deploying AI in DV for smarter and faster IP verification Arjumand Yaqoob - Qualcomm Incorporated |
Download | View | 15:30 | Doulos Know How Tutorial: Practical Asynchronous SystemVerilog Assertions |
| 15:30 | Practical Asynchronous SystemVerilog Assertions Doug Smith - Doulos |
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| 15:30 | Continuing Progress in Verification: A Mixed Signal Approach | ||
| 15:30 | Overcoming Obstacles to Model-based Verification Daniel Cross - Cadence Design Systems |
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| 15:50 | Modelling a 4-Level DCDC Converter Using EEnets Abhijit Madhu Kumar (On behalf of Paul Denny) - Cadence Design Systems |
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| 16:10 |
Practical Approaches to Adopting State of the Art Mixed Signal Solutions
Umar Lyles - Cirrus Logic |
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| 16:30 | Event Closes |
Sponsors
VF2025 was made possible through the generosity of the following sponsors. If you would like to become a VF2025 sponsor please Contact Us.
