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Verification Futures Conference 2023 US

The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.

Event at a Glance

Thursday, 14 September 2023 – Full day conference, exhibition and networking event

Austin Marriott South (US) and online

FREE to attend conference In-Person or Online


Call for Submissions

Abstracts are now being invited for talks at VF2023. Talks on a wide range of topical verification issues are invited, including, but not limited to, hardware verification, artificial intelligence and machine learning in verification, and verification of safety and security related designs.

Please visit VF2023 for guidance on the types of presentations that we are looking for.

Conference Program – Provisional

08:30 Arrival: Breakfast and Networking Slides Videos
09:25 Welcome: Mike Bartley, Tessolve Semiconductor Ltd
Keynote Speakers

Safety and Security challenges in hardware IP development

Vivek Vedula (Arm Ltd.)

User Top Verification Challenges

Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life

Alex Duhovich (Ericsson)


Speaker Name (Cadence)

11:00 Refreshments and Networking
Multi-Track Session (AM)
User Presentations

10 years of Verification Challenges

Mike Bartley, Tessolve


RISCV CPU Verification - Opportunities and Challenges

Divyang Agrawal, Tenstorrent


Validation of Hybrid Architectures

Suneil Mohan(Intel Corporation)

Track 2 - Training Session 1

What Can Formal Do For Me?

Doug Smith (Doulos)

12:30 Lunch and Networking

A Modern Fable: The Lost Art of Processor Verification

Larry Lapides (Imperas Software Ltd.)


Speaker Name (Breker) Gold Sponsor


Speaker Name (Company Name ) Gold Sponsor

14:40 Speaker Name (Company Name) Sponsor
15:00 Refreshments and Networking
Multi-Track Session (PM)
Track 1 - Latest topics in Verification

Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs

Aditya Devarakonda (NXP Semiconductor)




Session 2 – Speaker 3

Track 2 - Training Session 2

Using Non-Determinism with Formal

Doug Smith(Doulos)

16:30 Event Closes


VF2022 was made possible through the generosity of the following sponsors. If you would like to become a VF2022 sponsor please Contact Us.

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