The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.
Event at a Glance
Thursday, 14 September 2023 – Full day conference, exhibition and networking event
Austin Marriott South (US) and online
FREE to attend conference In-Person or Online
VF2023 Austin Event Programme
Conference Program
| 08:30 | Arrival: Breakfast and Networking | Slides | Videos |
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||
| Keynote Speakers | |||
| 09:30 | Safety and Security challenges in hardware IP development Vivek Vedula (Arm Ltd.) |
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| User Top Verification Challenges | |||
| 10:15 | Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life Alex Duhovich (Ericsson) |
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| 10:30 |
Bahadir Erimli(Cadence Design Systems) |
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| 11:00 | Refreshments and Networking | ||
| Multi-Track Session (AM) | |||
| User Presentations | |||
| 11:30 | 10 years of Verification Challenges Mike Bartley, Tessolve |
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| 11:40 | RISCV CPU Verification - Opportunities and Challenges Divyang Agrawal(Tenstorrent, Inc) |
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| 12:10 | Validation of Hybrid Architectures Suneil Mohan(Intel Corporation) |
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| Track 2 - Training Session 1 | |||
| 11:30 |
Doug Smith (Doulos) |
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| Track 3 - UVM for AMS Verification | |||
| 11:30 | Renesas’s Submission to the UVM-(A)MS working group Peter Grove , Steven Holloway (Renesas) |
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| 12:30 | Lunch and Networking | ||
| 13:30 | A Modern Fable: The Lost Art of Processor Verification Larry Lapides (Imperas Software Ltd.) |
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| 14:00 | Advanced RISC-V Verification Technique Learnings for SoC Validation Adnan Hamid (Breker Verification Systems) |
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| 14:20 | Improve the Quality of the Testbenches using specialized PySlint solutions Balram Naik Meghavath (Broadcom ltd.,) |
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| 14:40 |
Hemendra Talesara(Bitstar Technologies ) |
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| 15:00 | Refreshments and Networking | ||
| Multi-Track Session (PM) | |||
| Track 1 - Latest topics in Verification | |||
| 15:30 | Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs Aditya Devarakonda (NXP Semiconductor) |
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| 15:50 | DSP Verification Using MATLAB C Models Bill Tiffany (SigmaSense LLC) |
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| 16:10 | Methodology focused testbench generation Ben Delsol(UVMGen) |
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| Track 2 - Training Session 2 | |||
| 15:30 | Using Non-Determinism with Formal Doug Smith(Doulos) |
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| Track 3 - VHDL Verification | |||
| 15:30 | OSVVM in a NutShell, VHDL’s #1 Verification Methodology Jim Lewis(SynthWorks Design Inc) |
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| 16:30 | Event Closes |
Sponsors
VF2022 was made possible through the generosity of the following sponsors. If you would like to become a VF2022 sponsor please Contact Us.
