Advanced RISC-V Verification Technique Learnings for SoC Validation

The verification of application-level RISC-V cores require specialized techniques and approaches previously the purview of Arm, Intel and other processor companies. The open and customizable RISC-V cores have led to many new processor development teams with unique microarchitectural approaches that require extensive verification.

Breker has found that a key aspect of RISC-V core verification involves its smooth operation within the larger system. For example, load-store anomalies, asynchronous interrupt mechanisms, and security protocols are just a few of many issues that must be fully analysed. In developing new test approaches for these and other scenarios, their application in more general System-on-Chips has become apparent, and indeed these methods can track complex system corner cases that will never be detected simply by running real workloads or benchmarks.

This presentation will describe many techniques useful for RISC-V core verification, and also how they may be applied to the broader SoC at large for high coverage verification.

Adnan is the founder and CTO of Breker and the inventor of its core technology. Noted as the father of Portable Stimulus, he has over 20 years of experience in functional verification automation, much of it spent working in this domain. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor.

In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors. Adnan holds twelve patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.