||Verification Futures 2022 (click here to see full programme)
||SoC Verification in the post-Moore era
||The end of Moore scaling has driven SoC designs to include more and more parallel heterogeneous engines. This combined with the emergence of commercially viable chiplets and 3DICs means SoC architectures are becoming more varied. This presentation explores the verification challenges these new technologies present and how we can solve them.
||Nick Heaton is an ASIC and EDA veteran with more than 35 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honours in Engineering and Management Systems. Nick joined Cadence 15 years ago and is a Distinguished Engineer and SoC Verification Architect responsible for the new SystemVIP Product line.
- Emerging Soc architectures and their significance
- Performance predictability is becoming is big issue
- Verification Solutions are emerging to help address these challenges