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UVM War Stories

DVClub Europe Meeting – February 2018

Event at a Glance

Tuesday 6th February, 2018

11:30 – 14:00 GMT

FREE to attend In-Person or Online

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UVM War Stories

In this DVClub meeting our speakers will share their experiences adopting UVM (Universal Verification Methodology) and then open the floor for discussion followed by the usual networking opportunities.

The Universal Verification Methodology (UVM) is a standard to enable guaranteed development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. The Accellera industry body provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).

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Agenda (BST):

Time Session Description           Slides              Videos
11.30 GMT Arrival and Networking
12.00 GMT Welcome and Introduction

Mike Bartley, Senior Vice President – VLSI Design, Tessolve

12.05 GMT Functional Coverage is Useless

– Director of Processor Verification, Oracle

12.30 GMT I Didn’t Know Constraints Could Do That!

– John Dickol, Samsung Austin Research and Design Center

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12.55 GMT Coding High Performance UVM

– Mark Peryer, Mentor, a Siemens business

13.20 GMT Closing Remarks
13.30 GMT Networking

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.


DVCLUB Europe is made possible through the generosity of our sponsors.

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