|DVCLUB Europe | UVM War Stories
|Mark Peryer, VIP Architect, Mentor, a Siemens business
UVM continues to be the dominant testbench methodology into the foreseeable future. With the exponential increase in testbench complexity that comes from increasing design complexity, coding UVM for performance is growing ever more critical, whether you’re coding for simulation or planning to include emulation in your flow. Building on years of experience, user interactions and intimate knowledge of the inner workings of UVM (including the new IEEE 1800.2 version), Mark Peryer, VIP Architect at Mentor, a Siemens business, will share a number of tried and true coding techniques to help you get the most out of your UVM testbench. You’ll learn general performance enhancements, how to architect your testbench to make it emulation-friendly, and what to watch for in the new 1800.2 implementation of UVM.
|Mark Peryer led the Mentor Consulting verification practice in Europe for several years, working with major customers to introduce SystemVerilog testbench verification methodologies from AVM, OVM through UVM. More recently, Mark has worked as a member of the Verification Methodology team at Mentor, developing the UVM Cookbook and currently oversees the technical aspects of Verification IP development at Mentor. Along the way, he has architected many UVM testbench implementations informing a view on how to achieve performance.
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