|DVCLUB Europe | UVM War Stories
|John Dickol, Principal Engineer, Samsung Austin Research and Design Center
|Recent advances in SystemVerilog constraint solver performance make it practical to use more complex constraints in verification environments. This presentation will review some lesser-known SystemVerilog constraint features (soft constraints, hierarchical constraints, array reduction constraints) and provide working examples of using these and other features to create constrained stimulus for complex real-world CPU/SOC verification problems such as testbench configuration, memory map allocation, etc.
|John Dickol is a Principal Engineer at the Samsung Austin Research and Design Center (SARC) in Austin, Texas where he is currently developing verification tools and methodologies for GPU and CPU projects and looking for new ways to apply SystemVerilog constraints. Before joining SARC, he led verification teams for SOC and DSP projects at MediaTek, Analog Devices, Intel, and IBM. John has a BSEE from Lehigh University and a MSEE from Syracuse University. He has 5 U.S. patents.
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