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RISC-V SoC integration verification including system coherency. Is your RISC-V SoC-ready?

Conference: DVCLUB Europe | RISC-V Verification Strategies
Speaker: John Sotiropoulos, Breker Verification Systems Inc
Speaker Title: RISC-V SoC integration verification including system coherency. Is your RISC-V SoC-ready?
Abstract: RISC-V introduces a number of unique issues for modern SoCs, given the flexibility of its ISA and variations across different processor types and providers. This introduces verification challenges that must be considered both by end-users of the devices, as well as processor developers. As the RISC-V ISA is used for more complex processors and processor clusters, these problems are becoming more prevalent.

Breker’s engineers have been working with a number of RISC-V processor development teams as well as end-users. We have discovered and analysed issues specific to RISC-V as well as other processor types and produced an integration and coherency approach that appears to work well on these larger devices and applications. This talk will introduce the coherency algorithms and other techniques that can be employed on RISC-V SoCs, as well as on the processors themselves to check that they will behave correctly in a broad range of applications.

Also included is the efficient early test of RISC-V firmware at the block and sub-system level to ensure consistency from pre- to post-silicon, even given the use of custom instructions and novel architectures.

Key Points:

  • RISC-V introduces unique verification challenges for SoC integration and coherency that need to be tested by processor developers and end-users.
  • We introduce a range of algorithms and techniques used by developers and integrators alike to examine specialized RISC-V corner cases.
  • These solutions analyse coherency, firmware consistency, integration issues and other factors for devices with custom instructions and novel architectures.
Speaker Biography: John Sotiropoulos is a Principal Applications Engineer at Breker Systems. Prior to joining Breker, John began his AE journey at Synopsys, where he was exposed to the full gamut of verification tools and platforms used in our industry. He began his career as a verification engineer in the mid-90s and continued to work for a variety of companies including Intel, Facebook and Draper Labs. Projects worked on span from simple ASICs to CPUs and complex SoCs chips, used in both commercial and military applications.

John continues to be fascinated by the strides/progress made over the years in the verification realm, and strongly believes that verification has become a state-of-the-art discipline, as it combines the best of both hardware and software worlds. He holds a master’s degree in EE from Worcester Polytechnic Institute, and an MBA degree from Boston University.


DVCLUB Europe is made possible through the generosity of our sponsors.

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