|Conference:||DVCLUB Europe | Automated Verification Checks|
|Speaker:||Yassine Eben, Siemens EDA|
|Speaker Title:||Methodology for Increasing Continuous Integration Throughput|
|Abstract:||With designs increasing in size much faster than engineering headcount can be added, continuous integration is the best practice to automate RTL development and assure code quality is maintained throughout a project’s lifecycle. Furthermore, adding automated, exhaustive formal analysis of RTL code that doesn’t require a test bench is a perfect fit and becomes a key step in RTL development process from early design phase to late chip assembly stage.
This talk presents an easy-to-adopt methodology to maximize continuous integration throughput for better code quality and focused debug, including prioritization techniques for formal automated check classes.Key Points:
|Speaker Biography:||Yassine Eben-Aimine is a Senior Applications Engineer at Siemens EDA with over 20 years’ experience in EDA software technical account management, technical marketing; guiding customers through hands-on product evaluations and deployments. Yassine holds bachelors and masters degrees in Electronics and Computing from the Institute National Polytechnique (ENSEEIHT) in Toulouse, France|
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