Event at a Glance
Tuesday 08th September, 2020
12:00 – 13:30 GMT
FREE to attend Online
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IP Integration Into Complex SoCs
SoC designs typically incorporate a range of (in-house and external) IP, all connected via different bus structures. In this DVClub we consider the effectiveness and efficiency of different verification techniques to ensure the IP has been correctly integrated
|12.00 GMT 17:30 IST||
Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
|12.05 GMT 17:35 IST||
IP Integration Verification in Extra-large (XL) SoCs
Sergio Marchese, Technical Marketing Manager, OneSpin Solutions
|12.25 GMT 17:55 IST||
Solving system-level challenges of integrating PCIe gen 4 RC IP
Nick Heaton, Distinguished Engineer, Cadence
|12.45 GMT 18:15 IST||
Power Control Verification Challenges In Arm-based SoCs
Deepak Joshi, Staff Verification Engineer, ARM Ltd.
|13.05 GMT 18:35 IST||
Verification and Integration challenges in RISC-V SOC
Suresh babu Pushparajan, Director, Tessolve
|13.25 GMT 18:55 IST||Closing Remarks|
|13.30 GMT 19:00 IST||Close|
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
DVCLUB Europe is made possible through the generosity of our sponsors.