Skip to main content

Solving system-level challenges of integrating PCIe gen 4 RC IP

Conference: DVCLUB Europe | IP Integration Into Complex SoCs
Speaker: Nick Heaton, Distinguished Engineer, Cadence

PCIe gen3 and beyond added a number of complex system level protocols for enhancing system performance. This presentation will show how Portable Stimulus can rapidly accelerate the complex task of integration verification of such IP.

3 Key Points:

  • IP only verification is insufficient, growing need for system-level verification
  • Portable Stimulus enables plug-and-play system-level verification
  • Performance Verification is a growing challenge in System Verification
Speaker Biography: Nick graduated with 1st Class Honours in Special Engineering from Brunel University in 1983. He worked for 15 years in SoC Design and then moved into advanced Verification. Nick works in Cadence System and Verification RnD Group and is responsible for SoC Verification.


DVCLUB Europe is made possible through the generosity of our sponsors.

Close Menu