Event at a Glance
Tuesday 15th, May, 2018
11:30 – 14:00 BST
FREE to attend In-Person or Online
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Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting our speakers will share their experiences adopting Formal Verification and then open the floor for discussion followed by the usual networking opportunities.
|11.30 BST||Arrival and Networking|
|12.00 BST||Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
|12.05 BST||Deep Formal Methodology for Arm Austin’s A-class CPUs: Evolution and Learnings
Vikram Khosa, Principal Engineer, Arm
|12.30 BST||Two Case Studies in Formal Deployment on ARM CPUs : Instruction-Fetch and Floating-Point Datapath
Vaibhav Agrawal, Principal Engineer, Arm
|12.55 BST||Meeting the Challenge: Formal Verification of an FPU
Nicolae Tusinschi, Product Specialist Design Verification. OneSpin Solutions
|13.10 BST||It’s Been 24 Hours – Should I Kill My Formal Run?
Jeremy Levitt, Principal Engineer, Questa Formal R&D, Mentor, A Siemens Business
|13.25 BST||Closing Remarks|
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
DVCLUB Europe is made possible through the generosity of our sponsors.