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Alternative Test Bench Architectures

DVClub Europe Meeting – May 2022

Event at a Glance

Tuesday 17th May, 2022

12:00 – 13:10 BST

FREE to attend Online

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Alternative Test Bench Architectures

Four verification experts will spend 20 minutes outlining tools and methodologies aimed at using Alternative Test Bench Architectures.

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Agenda (BST):

Time Session Description           Slides              Videos
12.00 BST 16:30 IST Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12.05 BST 16:35 IST Decoupling Generation and Simulation in an IP Test Bench
Tim Blackmore, Infineon Technologies Ltd
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12.25 BST 16:55 IST ADAS IP Case Study: De-Coupled Generation and Simulation for Functional Verification
Rhys Hodson, Infineon Technologies Ltd
Download View
12.45 BST 17:15  IST Top down, UVM-style testbenches with PSS David Kelf, Breker Verification System Download View
13.05 BST 17:35 IST Closing Remarks
13.10 BST  17:40 IST Close

About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.


DVCLUB Europe is made possible through the generosity of our sponsors.

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