|Conference:||DVCLUB Europe | Alternative Test Bench Architectures|
|Speaker:||Tim Blackmore, Infineon Technologies Ltd|
|Speaker Title:||Decoupling Generation and Simulation in an IP Test Bench|
In a standard IP verification environment, generation and simulation are closely coupled so that after simulation there is no artefact of the stimuli applied to the DUT other than test and seed. In an executing project this can lead to problems such as random instability. To avoid such problems, we have implemented verification environments where generation and simulation are decoupled. The approach is easily tailored to overcome drawbacks and comes with a number of side benefits.
|Speaker Biography:||Tim is a Senior Principal Verification Engineer at Infineon Technologies, based in Bristol. His research focus is improving the efficiency of the verification of complex IPs, subsystems and SoCs including by the use of machine learning. He is also the Global Verification Manager for Infineon’s current family of Aurix3G microcontrollers and is a Visiting Industrial fellow at the University of Bristol.|
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