|DVCLUB Europe | Alternative Test Bench Architectures
|David Kelf, Breker Verification Systems
|Top down, UVM-style testbenches with PSS
|UVM on top of SystemVerilog has become ubiquitous for block-based verification test content. Although it provides many enhancements for common test bench reuse as well as an effective framework for advanced constrained random testing, fundamentally, UVM is still a somewhat “bottoms-up” approach. Given its complexity, UVM test content does not scale well for larger blocks or sub-systems, and it is relatively unusable for full SoCs. Portable Stimulus enables top-down techniques but requires a steeper language learning curve. This presentation will look at how a UVM class library and utilities may be added to PSS to enable a specification-based, top-down methodology on top of existing UVM testbenches, while retaining familiar UVM constructs and use models to improve ease-of-use.
|David Kelf, is the Chief Executive Officer at Breker Verification Systems and has been with the company four years as CEO and formerly in the VP Marketing role. Previous to Breker, Dave most recently served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier, Kelf was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys.
Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.
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