Verification & Semiconductor
The premier forum for VLSI design and verification engineers, researchers,
and vendors to discuss challenges, shape practical solutions and define
verification and semiconductor futures.
Date & Time
Thursday, 08 October 2026
9:30 AM- 4:30 PM
Location
Sonesta San Jose – Milpitas, 777 Bellew Dr, Milpitas, CA 95035, United States
Format
In-person & Online
The Semiconductor Ecosystem –
From Design to Verification
Verification Futures San Jose 2026, co-located with Semiconductor Futures 2026, delivers a unique blend of
conference presentations, exhibitions, training, and industry networking.
Advanced EDA Tools & Technologies
Latest Research From Universities
Expert Talks
& Training
Product & Engineering
Experts
Multiple Tracks
Event Schedule
Thursday, 08 Oct 2026 — Full Day Conference
09:30
Registration, Breakfast & Networking
10:15
Welcome Note – Mike Bartley, Alpinum Consulting
10:20
Pre-Keynote – Tessolve
10:30
Keynote – Sean Safarpour, AMD
Parallel
11:00
Formal Verification and AI
Tobias Ludwig,
LUBIS EDA
CDC-RDC Verification Tutorial
Bill Gascoyne,
Blue Pearl Solutions
Dammy Olopade
Google
Parallel
11:30
Formal Verification and AI
Shankar Channabasappa,
Tessolve Semiconductor Inc
CDC-RDC Verification Tutorial
Bill Gascoyne,
Blue Pearl Solutions
Dammy Olopade
Google
Parallel
11:50
Formal Verification and AI
Nayab Hossain,
Chipster
CDC-RDC Verification Tutorial
Bill Gascoyne,
Blue Pearl Solutions
Dammy Olopade
Google
Parallel
12:10
Formal Verification and AI
Ankit Kumar Garg,
Formal Verification
CDC-RDC Verification Tutorial
Bill Gascoyne,
Blue Pearl Solutions
Dammy Olopade
Google
12:30
Lunch & Networking
Parallel
13:30
Using AI and Open Source in DV
Andy Bond,
OLIX
Emerging Hardware Technologies
Gurpreet S Kalsi,
Intel
Parallel
14:00
Using AI and Open Source in DV
Sasa Stamenkovic,
Pure Silicon Solutions
Emerging Hardware Technologies
Frank Schirrmeister,
Synopsys
Parallel
14:20
Using AI and Open Source in DV
Suraj Chakravarthi Raja,
MathWorks, Inc.
Emerging Hardware Technologies
Allen Nejah,
SunMan Engineering, Inc.
Parallel
14:40
Using AI and Open Source in DV
Oscar Gustafsson,
Linköping University
Emerging Hardware Technologies
Abyarthana Bisoyi,
Odisha University of Technology and Research
15:00
Refreshment Break & Networking
Parallel
15:30
Verifying Complex Systems
Chiranjeevi Sirandas,
NVIDIA
AMS Design and Verification
Leon King,
Cadence Design Systems
Parallel
15:50
Verifying Complex Systems
Sivaharan Janahan,
WRAXK Corp.
AMS Design and Verification
Leon King,
Cadence Design Systems
Parallel
16:10
Verifying Complex Systems
Krupa Shah,
Cisco Systems, Inc.
AMS Design and Verification
Sandeep Sharma,
Meta
Vijay Akkaraju,
Cadence Design Systems
16:30
Closing Networking Reception
11:00
AI Design IP
Levon Khachatryan,
Voskenai Ltd
11:30
AI Design IP
Alexander Montgomerie-Corcoran,
Heronic Technologies
11:50
AI Design IP
Greg Chadwick,
Fractile
12:10
AI Design IP
James Lewis,
RED Semiconductor International Ltd
12:30
Lunch — Exhibition & Networking
Parallel
13.30
Design
Valentin Peltier,
Secure-IC – A Cadence company
FPGA
Yassine Eben Aimine,
Siemens
Parallel
14:40
Design
John Darlington,
Arm and the University of Southampton
FPGA
Rojalin Mishra,
Riverlane
15:00
Break — Exhibition & Networking
Parallel
15:30
Startups and Breakthrough Technologies
Francesco Raffaelli,
KETS Quantum Security Ltd
FPGA
Phill Payne,
Novomorphic
Parallel
15:50
Startups and Breakthrough Technologies
Prof. Rob Young,
Quantum base
FPGA
Simon Southwell,
Wyvern Semiconductors
Parallel
16:10
Startups and Breakthrough Technologies
TBD
FPGA
Simon Southwell,
Wyvern Semiconductors
16:30
Drinks & Pizza Networking
17:00
Conference Ends
Speaker Lineup
Industry leaders, researchers, and innovators shaping the future of verification.
Ankit Kumar Garg
Senior Manager, Formal Verification ,
NVIDIA
Tobias Ludwig
CEO,
LUBIS EDA
Andy Bond
Director RTL and Verification,
OLIX
Shankar Channabasappa
AVP Custom Silicon,
Tessolve Semiconductor Inc
Nayab Hossain
CEO,
Chipster
Krupa Shah
ASIC Engineering, Technical Leader,
Cisco Systems, Inc.
Our Sponsors
Verification Futures 2026 is made possible by the generous support of our
sponsors and exhibitors.
Become a Sponsor
Sponsor packages are available for VF2026 Austin. Reach
the verification and semiconductor community —
engineers, researchers, and decision-makers.
