Vikash Kumar

About the Speaker

Vikash Kumar is a Senior Verification Architect at Arm and an IEEE Senior Member with over 15 years in the semiconductor industry, specializing in the verification of complex designs across IP, subsystem, and full SoC levels using SystemVerilog and UVM. He is the author of the forthcoming Springer book AI-Assisted Hardware Verification: Cognitive Verification Architecture with the VEGA Framework. His work focuses on large-scale SoC integration and verification closure, with deep experience in AMBA, CHI, PCIe, and UCIe. Prior to Arm, he held roles at Intel, contributing to silicon programs including the Intel Data Streaming and Analytics Accelerators.

Trustworthy Shift-Left Integration Strategies Using AI to Accelerate SoC Verification

Overview

Shift-left stalls because the verification environment lands too late. AI can collapse that timeline, generating the driver, monitor, scoreboard, sequences, and coverage from the spec in hours. But early and fast is worthless if the generated environment is hollow, because that just shifts false confidence left. This talk shows a VEGA-framework approach. AI generation is anchored to machine-readable intent, then a tool-agnostic metric set scores stimulus quality, checking integrity, and observability before the environment is trusted. Calibrated against a hand-built environment on the same block, the metrics become something you can actually gate a shift-left flow on.

Key Points

• AI can shift verification genuinely left, but a generated testbench that runs and closes coverage can still be hollow, shifting false confidence left instead of real verification.
• VEGA scores quality on three tool-agnostic properties: stimulus coverage of the legal input space, whether every checker can actually fail, and whether the environment can see an injected defect.
• Calibrating the metrics against a known-good hand-built testbench turns them from opinion into a gate you can trust a shift-left flow on.