|Conference:||DVCLUB Europe | Universal Verification Methodology (UVM)|
|Speaker:||Mark Handover, Digital Design and Verification Solutions , Mentor, A Siemens Business|
|Abstract:||As designs continue to grow in complexity, the testbenches to verify those designs are growing right along with them. A recent study shows that, on average, verification engineers spend more time on debug than on any other task, including creating and running the tests. This session will show you how to navigate complex UVM environments, quickly find your way around the code, whether your own or inherited. Learn how to see what’s going on in your testbench, how to debug dynamic class activity in SV/UVM alongside RTL signals.|
|Speaker Biography:||Mark has been involved in the design & verification of complex SoC’s for over 20 years with positions in a number of commercial and mil-aero companies. In his current role as an applications engineer with Mentor, a Siemens Business, his work involves supporting customers as they adopt and deploy advanced functional verification solutions.
His specialties include formal, clock-domain crossing, static verification, low power and advanced debug.
DVCLUB Europe is made possible through the generosity of our sponsors.