Event at a Glance
Tuesday 5th February, 2019
11:30 – 14:00 BST
FREE to attend In-Person or Online
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The Universal Verification Methodology (UVM)
In this DVClub meeting our speakers will share their experiences of using UVM (the Universal Verification Methodology) and then open the floor for discussion followed by the usual networking opportunities.The Universal Verification Methodology (UVM) is an Accellera standard to enable both the development and reuse of verification environments and verification IP (VIP) throughout the electronics industry. The Accellera industry body provides both an API standard for UVM and a reference implementation. That reference implementation is a class library defined using the syntax and semantics of SystemVerilog (IEEE 1800).
|11.30 BST||Arrival and Networking|
|11.55 BST||Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
|12.00 BST||UVM Register Map Dynamic Configuration
Matteo Barbati, Senior Digital Verification Engineer, STMicroelectronics
|12.30 BST||Generating Bus Traffic Patterns
Jacob Sander Andersen, CTO, SyoSil ApS
|13.00 BST||Common UVM Register Model Issues and Pitfalls
Uwe Simm, Architect, Cadence
|13.20 BST||Advanced UVM Debug
Mark Handover, Digital Design and Verification Solutions, Mentor, A Siemens Business
|13.35 BST||Close and Networking|
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
DVCLUB Europe is made possible through the generosity of our sponsors.