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Common UVM Register Model Issues and Pitfalls

Conference: DVCLUB Europe | Universal Verification Methodology (UVM)
Speaker: Uwe Simm, Architect, Cadence
Abstract: The UVM register model is the biggest part within the UVM implementation. While the usage in module level UVM environments is more or less seamless the application of the register model has numerous issues and pitfalls when it comes to subsystem or system usage. The talk outlines several issues and problems present in the current code base so that engineers can avoid problematic areas …
Speaker Biography: Uwe works as a Solution Architect for the Cadence Verification Division with almost 20 years experience in design, implementation and verification of complex chip designs in various companies. Over the years he has been exposed to various tools in the analog and digital simulation world, languages (VHDL, SystemVerilog, SystemC, Specman/e), programming concepts and methodologies.
He is currently focusing upon verification efficiency and UVM-SystemVerilog and has been contributing to the development of UVM since the UVM10.


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