|DVCLUB Europe | Universal Verification Methodology (UVM)
|Matteo Barbati, Senior Digital Verification Engineer, STMicroelectronics
|The UVM register map provides data structures and testsuites that allow checking the data integrity of the DUT register map during simulations. This object can be extended to allow the synchronization between the register model and any verification component present in the environment. Beside ad-hoc approaches based on code customization or custom code generation from IP-XACT, we present a solution that simplifies and automatizes such interaction.
|Matteo Barbati has received his Master Degree in Computer Science at “Politecnico di Milano” in 2005. After a brief experience as Researcher at “Politecnico di Milano” he started to work in STMicroelectronics in 2006 with the role of IP Verification Engineer.
In 2011 he started to work as Digital Designer in Yogitech and he returned in ST as SerDes Digital Designer. In 2015 he moved to SerDes Verification Team with the role of Verification Engineer focused on High-Speed IP Verification.
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