|Conference:||DVCLUB Europe | Universal Verification Methodology (UVM)|
|Speaker:||Jacob Sander Andersen, CTO, SyoSil ApS|
During the block level verification of the modules in an ASIC using SystemVerilog with the UVM methodology we were required to generate specific traffic patterns for a bus protocol as requested by the architect
(design engineers, system architect, etc.). Particularly the specification of the traffic pattern was problematic, as it was ambiguous and could be interpreted differently by the architect and the verification engineers. For improved reusability across various verification environments and platforms the traffic patterns could instead be accurately expressed by using a domain specific language (DSL). The DSL could then easily be converted into executable code for producing the expected traffic patterns.
As the SyoSil CTO, Jacob governs SyoSil’s technical lead in the ASIC verification domain. Jacob also acts as the responsible architect for SyoSil’s generation framework, targeting generation of UVM UVCs and verification environments. Jacob has authored and co-authored multiple publications on these topics.
Jacob holds a M. Sc. CS. from the Technical University of Denmark, 2001.
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