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Latest VHDL Verification Techniques

 DVClub Europe Meeting – April 9

Event at a Glance

Tuesday  9 th  April , 2024

13:00 to 14:00 (BST)

FREE to attend Online

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Latest VHDL Verification Techniques

This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM

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Agenda (BST):

Time Session Description Slides Videos
13.00 BST

Welcome and Introduction

Mike Bartley,Tessolve

13.00 BST

Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage)

Espen Tallaksen, EmLogic

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13.30 BST

OSVVM in a NutShell, VHDL’s #1 Verification Methodology

Jim Lewis, SynthWorks Design Inc

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14.00 BST

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About DVClub

The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.

Sponsors

DVCLUB Europe is made possible through the generosity of our sponsors.

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