Verification & Semiconductors
The premier forum for VLSI design and verification engineers, researchers,
and vendors to discuss challenges, shape practical solutions and define
verification and semiconductor futures.
Tuesday, 23 June 2026
9 am – 4.30 pm
University of Reading (UK)
In-person & Online
The Semiconductor Ecosystem –
From Design to Verification
Verification Futures UK 2026, co-located with Semiconductors Futures 2026, delivers a unique blend of
conference presentations, exhibitions, training, and industry networking.
Verification Futures
Formal methods for complex SoCs, CPU & RISC-V verification, open-source tools, AI in DV, verification planning & coverage, and HW/SW co-verification.
Formal Methods
RISC-V
AI in DV
Coverage
Co-Verification
Semiconductors Futures
AI/ML in IP & SoC design, EDA workflows, FPGA, automotive, quantum computing, photonics, and chiplets.
Engineering Students
50+ students with UKESF-supported presentations, mentoring, and career pathways.
Hybrid
Attend in-person at Reading, UK or join online — conference, exhibition, training, and networking.
University of Reading (UK)
& Online
Advanced EDA Tools & Technologies
Latest Research From Universities
40+ Expert Talks
& Training
Product & Engineering
Experts
10+ Tracks
Event Schedule
Tuesday, 23 June 2026 — Full Day Conference
Special Student Track — UKESF
A dedicated programme for engineering students runs from 11:00 – 16:30, featuring presentations, mentoring, and career pathways.
08:30
Exhibition Opens — Student posters available for viewing
09:25
Conference Starts — Welcome and introductions
09:30
Keynote Address — Ekaterina Almasque — Blank Page Capital
10:00
Platinum Sponsor Presentation — Kartik Hegde — Cadence
10:30
Break — Exhibition & Networking
Latest Verification Methods
Dr. Tobias Ludwig,
LUBIS EDA
Verification Projects using Open Source/License-Free Tools
Alpinum
Latest Verification Methods
Surinder Sood,
ARM
Verification Projects using Open Source/License-Free Tools
Jerome Sauger,
AXELERA AI
Latest Verification Methods
Christian Appold,
Denso
Verification Projects using Open Source/License-Free Tools
Doug Carson,
Keysight Technologies
Lunch — Exhibition & Networking
Mixed Signal
Ahmed Fergany
Mixed Signal
Cadence
Mixed Signal
Siemens
Afternoon Verification Session
Siemens
Mixed Signals
Thalia Design Automation
Break — Exhibition & Networking
Main Afternoon
Abhyarthana Bisoyi,
Odisha University of Technology and Research
AI in DV
Abdulrahman Elsadiq,
Alpinum consulting
Main Afternoon
Katharina Ceesay-Seitz,
ETH Zurich
AI in DV
Shivayogi Kerudi,
Tessolve
Main Afternoon
Abinaya Sentil,
Silicondv
AI in DV
Ramesh Krishnamurthy,
APRIL AI Hub Research
Drinks & Pizza Networking
Conference Ends
AI Design IP
Cadence
AI Design IP
Alexander Montgomerie-Corcoran,
Heronic Technologies
AI Design IP
Bragadeesh S,
Tattvam AI
Lunch — Exhibition & Networking
Design
Valentin Peltier,
Cadence
FPGA Topic
Siemens
FPGA Topic
Simon Southwell,
Wyvern Semiconductors
Design
Doug Carson,
Keysight Technologies
Break — Exhibition & Networking
Startups and Breakthrough Technologies
Francesco Raffaelli,
KETS Quantum Security Ltd
Design for Test
Sameer Saran,
Siltest
Design for Test
Siemens
Drinks & Pizza Networking
Conference Ends
Speaker Lineup
Industry leaders, researchers, and innovators shaping the future of verification.
Kartik Hegde
Sr Group Director,
Cadence
Dr. Tobias Ludwig
CEO,
LUBIS EDA
Ekaterina Almasque
Co-founder & Managing Partner,
BlankPage Capital
Doug Carson
Solution Expert,
Keysight
Abhyarthana Bisoyi
Assistant Professor,
Odisha University of Technology and Research
Dr Ramesh Krishnamurthy
Postdoctoral Research Associate,
University of Edinburgh
Our Sponsors
Verification Futures 2026 is made possible by the generous support of our
sponsors and exhibitors.
Become a Sponsor
Sponsor packages are available for VF2026 UK. Reach
the verification and semiconductor community —
engineers, researchers, and decision-makers.
