Verification & Semiconductor
The premier forum for VLSI design and verification engineers, researchers,
and vendors to discuss challenges, shape practical solutions and define
verification and semiconductor futures.
Date & Time
Tuesday, 06 October 2026
8:30 AM – 5:00 PM
Location
Hilton Austin Airport, 9515 Hotel Dr, Austin, TX 78719, United States
Format
In-person & Online
The Semiconductor Ecosystem –
From Design to Verification
Verification Futures Austin 2026, co-located with Semiconductor Futures 2026, delivers a unique blend of
conference presentations, exhibitions, training, and industry networking.
Advanced EDA Tools & Technologies
Latest Research From Universities
Expert Talks
& Training
Product & Engineering
Experts
Multiple Tracks
Event Schedule
Tuesday, 06 Oct 2026 — Full Day Conference
08:30
Registration
09:25
Welcome
09:30
Keynote
Irene Deng,
NXP Semiconductors
10:00
Platinum Sponsor
10:30
Refreshment Break & Networking
Parallel
11:00
Formal Verification
Tobias Ludwig,
LUBIS EDA
Open Source EDA Verification tools
Andy Bond,
OLIX
CDC-RDC Verification Tutorial
TBD
Parallel
11:30
Formal Verification
Shankar Channabasappa,
Tessolve Semiconductor Inc
Open Source EDA Verification tools
TBD
CDC-RDC Verification Tutorial
TBD
Parallel
11:50
Formal Verification
David Landoll,
Siemens
Open Source EDA Verification tools
CDC-RDC Verification Tutorial
TBD
Parallel
12:10
Formal Verification
TBD
Open Source EDA Verification tools
CDC-RDC Verification Tutorial
TBD
12:30
Lunch — Break & Networking
Parallel
13:30
Using AI in VLSI & DV
Sunil Sahoo,
Siemens EDA
Open Source EDA design tools
TBD
AMS Design and Verification
TBD
Parallel
14:00
Using AI in VLSI & DV
Abinaya,
NXP Semiconductors
Open Source EDA design tools
TBD
AMS Design and Verification
TBD
Parallel
14:20
Using AI in VLSI & DV
Vikash Kumar,
ARM
Open Source EDA design tools
TBD
AMS Design and Verification
Daniel Cross,
Cadence Design Systems
Parallel
14:40
Using AI in VLSI & DV
Frank Schirrmeister,
Synopsys
Open Source EDA design tools
TBD
AMS Design and Verification
TBD
15:00
Refreshment Break & Networking
Parallel
15:30
Using AI in DV
Vinoth Selvan,
NVIDIA Corporation
Emerging Hardware Technologies
TBD
Using AI in VLSI Flows
TBD
Parallel
15:50
Using AI in DV
TBD
Emerging Hardware Technologies
TBD
Using AI in VLSI Flows
Tom Henige,
MathWorks, Inc.
Parallel
16:10
Using AI in DV
Shelly Henry,
Moores Lab AI
Emerging Hardware Technologies
Jagadish Rongali,
NXP Semiconductors Inc
Using AI in VLSI Flows
TBD
16:30
Closing Networking Reception
11:00
AI Design IP
Levon Khachatryan,
Voskenai Ltd
11:30
AI Design IP
Alexander Montgomerie-Corcoran,
Heronic Technologies
11:50
AI Design IP
Greg Chadwick,
Fractile
12:10
AI Design IP
James Lewis,
RED Semiconductor International Ltd
12:30
Lunch — Exhibition & Networking
Parallel
13.30
Design
Valentin Peltier,
Secure-IC – A Cadence company
FPGA
Yassine Eben Aimine,
Siemens
Parallel
14:40
Design
John Darlington,
Arm and the University of Southampton
FPGA
Rojalin Mishra,
Riverlane
15:00
Break — Exhibition & Networking
Parallel
15:30
Startups and Breakthrough Technologies
Francesco Raffaelli,
KETS Quantum Security Ltd
FPGA
Phill Payne,
Novomorphic
Parallel
15:50
Startups and Breakthrough Technologies
Prof. Rob Young,
Quantum base
FPGA
Simon Southwell,
Wyvern Semiconductors
Parallel
16:10
Startups and Breakthrough Technologies
TBD
FPGA
Simon Southwell,
Wyvern Semiconductors
16:30
Drinks & Pizza Networking
17:00
Conference Ends
Speaker Lineup
Industry leaders, researchers, and innovators shaping the future of verification.
Tobias Ludwig
CEO,
LUBIS EDA
Andy Bond
Director RTL and Verification,
OLIX
Vikash Kumar
Senior Verification Architect,
Arm
Daniel Cross
Solutions Architect,
Cadence Design Systems
David Landoll
Product Manager, Questa Static & Formal Solutions,
Siemens
Sunil Sahoo
Product Manager,
Siemens EDA
Our Sponsors
Verification Futures 2026 is made possible by the generous support of our
sponsors and exhibitors.
Become a Sponsor
Sponsor packages are available for VF2026 Austin. Reach
the verification and semiconductor community —
engineers, researchers, and decision-makers.
