Verification Futures » VF2025 UK » Validate and Implement a RISC-V core using AI

Validate and Implement a RISC-V core using AI

Conference:	Verification Futures 2025 (click here to see full programme)
Speaker:	Vidushi Yaksh, William Ly
Presentation Title:	Validate and Implement a RISC-V core using AI
Abstract:	This project validated and implemented a RISC-V core using AI, focusing on distinct verification and implementation phases. Verification aimed to explore verification flow and conduct coverage analysis of a Bluespec MCU SoC. The implementation phase involved creating a baseline RISC-V core design using Synopsys Fusion Compiler™, which was subsequently optimized for Power, Performance, and Area (PPA) with Synopsys DSO.ai™ by exploring search space with custom permutons. This resulted in 2 separate designs; one running at a 500MHz frequency with power and area significantly under target PPA requirements, and another running at 1GHz with higher power and area metrics while still conforming to target PPA requirements.
Speaker Bio:	Vidushi Yaksh: 4th year student studying MEng Electronic Engineering with Computer Systems William Ly: 4th year student studying MEng Electrical and Electronic Engineering
Key Points:	Enhanced Design Through AI Optimization Starting from a Fusion Compiler™ baseline, we used DSO.ai™ to explore the design space and achieved improved PPA, meeting targets at 500 MHz and enabling operation at 1 GHz within power and area constraints. Custom Metric-Driven Reinforcement Learning We defined custom metrics to guide DSO.ai™’s reinforcement learning, enabling targeted optimization across multiple flow stages. Improved Efficiency and Design Quality DSO.ai™ significantly reduced manual tuning effort and identified optimal configurations beyond those found through conventional methods.