Navigating the Verification Maze

There are multiple languages and techniques available for verifying a digital logic FPGA or IC. You could just write a basic testbench in VHDL or Verilog/SystemVerilog. You could write a sophisticated testbench in either language using Transaction Level Verification (TLV). You could use Constrained Random Verification. You could even adopt one of these two completely different approaches: Formal Verification and/or the Portable Stimulus Standard (PSS). It's a maze. What best to do? Which path to take? This presentation helps you navigate this Verification Maze by introducing these languages and techniques, what they are, what they are for, and how to choose between them.

Matthew Taylor has been a key member of the Doulos technical team since 2014, specialising in Hardware Description Language-based design and verification, formal verification, and digital hardware design. As well as developing, writing, and presenting training courses and webinars, Matthew is responsible for the day-to-day running and development of the EDA Playground website, owned by Doulos. He is also an Employee Trustee of Doulos, an employee-owned company. Matthew has an MEng in Electrical and Electronic Engineering and holds patents for 25 inventions in digital TV demodulation across 40 countries and regions.

Before joining Doulos, Matthew worked at Sony for 16 years where he designed and managed the development of ICs (for digital TV and mobile phones) and designed algorithms for digital TV demodulation. Before that, he worked at Siemens (Roke Manor) where he designed FPGA/ICs and embedded software for various radio systems. He has 35 years of experience in electronics design and verification.