Automating Cyber-physical Security Verification in the SoC Design Flow

As security certification becomes essential for AI and embedded SoCs, verifying resistance to side-channel attacks (e.g., power or electromagnetic analysis) is now a critical part of the verification flow. This presentation introduces Secure-IC’s Laboryzr™, which automates side-channel vulnerability assessment from early design stages through silicon validation. We will demonstrate how Laboryzr™ integrates with existing verification workflows to apply leakage detection techniques such as TVLA and CPA, using standardized stimuli and automated result interpretation. The session will detail how this methodology accelerates compliance with certification schemes such as Common Criteria and CAVP, reduces human error, and helps close the security verification gap prior to tape-out.

Valentin Peltier joined Secure-IC in 2013 as an engineer. After a decade of technical experience, he transitioned in 2023 to the product team. He currently contributes to the development and ongoing management of the product catalog for Laboryzr, one of Secure-IC’s key business lines.