Advanced RISC-V Virtualizer/Hypervisor Verification for CPU & SoC

The advent of RISC-V has presented verification teams with many new challenges. As we move towards more system-level verification and RISC-V Application Processors in general, these types of scenarios will become commonplace. This presentation will discuss a specific complex, but yet commonplace, verification challenge for any team working on a complex RISC-V core, demonstrating the types of scenarios included in the Breker RISC-V SystemVIPs. We will consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The presentation will contain valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC. It will also demonstrate techniques for the verification of complex system scenarios in general.

Dave Kelf, is the CEO of Breker Verification Systems, the leader in test suite synthesis and SystemVIPs. Previously, Dave served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier, Kelf was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys. Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.