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Extending riscv-dv to suit your specific needs

Conference: Verification Futures 2024 (click here to see full programme)
Speaker: Mike Thompson
Presentation Title: Extending riscv-dv to suit your specific needs.

The OpenHW Group has been using the Chips Alliance “riscv-dv” pseudo-random instruction stream generator to verify its CORE-V family of RISC-V cores since 2020. Each core has specific freatures that may not be supported by a general-purpose tool.

Speaker Bio:

Mike is a functional verification engineer and manager who has been involved in all aspects of the discipline: simulation, emulation, prototyping and formal verification. He is strong proponent of coverage driven processes in the pursuit of first-time-right silicon.

Key Points:
  • Riscv-dv is an open-source project maintained by the Chips Alliance.
  • The OpenHW verification environment uses the SystemVerilog/UVM implementation of riscv-dv.
  • Core-specific behaviors are added to riscv-dv as a set of SystemVerilog class extensions. The base code of riscv-dv is not modified.
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