Pushing forward the frontiers of formal in Arm CPUs

Conference:	Verification Futures 2024 (click here to see full programme)
Speaker:	Vikram Khosa
Presentation Title:	Pushing forward the frontiers of formal in Arm CPUs
Abstract:	Over the last decade, formal verification has been steadily maturing into a mainstream methodology and seeing serious adoption across various semiconductor companies, including Arm. However, the long-held promise of being able to deploy formal to exhaustively verify designs in a timely manner is still limited by size, complexity, and cost of compute. In addition, opportunities for novel formal use-cases are also tempered by their own fresh set of challenges. This talk covers some of these challenges and the innovative solutions being developed to address the twin demands of convergence and efficiency.
Speaker Bio:	Vikram Khosa has been spearheading initiatives in formal methodology as well as involved in hands-on deployment of formal methods for functional and security verification, across various roles in A-class CPU design projects, at Arm’s Austin design center since 2013. Previously, he led memory-system verification for the Cortex A15 CPU. He has also worked in various verification roles for other companies, including 2 early-stage start-ups. He holds a master’s in computer engineering from the University of Minnesota, Twin Cities and a B.E. (Hons.) from BITS Pilani.
Key Points:	Formal is now a mainstream methodology at several hardware companies including Arm. However, formal deployment is still limited by size and complexity of designs, alongside cost of compute. We discuss these challenges and efforts at solving them across Arm CPU formal teams.

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

AI chips must get the math right

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification

3 Key Points:

Floating-point unit (FPU) for AI chips

FPU Formal Verification App

Compliance with IEEE-754

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

Pushing forward the frontiers of formal in Arm CPUs

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ML Verification Turns Convention on its Head

An Emulation Strategy for Artificial Intelligence Designs

AI chips must get the math right

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