The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.
Event at a Glance
Thursday, 12 September 2024 – Full day conference, exhibition and networking event
Austin Marriott South (USA) and online
FREE to attend conference In-Person or Online
VF2024 Austin Event Programme
Conference Program
| 08:30 | Arrival: Breakfast and Networking | Slides | Videos |
| 09:25 | Welcome: Mike Bartley, Tessolve Semiconductor Ltd | ||
| Keynote Speakers | |||
| 09:30 | Rethinking Verification Leadership: Ready or Not, Here Comes Generative AI Hemendra Talesara ,Startups (Bitstar Technologies, Planorama Design, others) |
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| 10:15 | User Top Verification Challenges | ||
| 10:15 | Challenges in Verification for Automotive Applications Vijay Kanumuri (Renesas Electronics) |
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| 10:30 | AI and GenAI for Verification Productivity Paul Graykowski(Cadence Design Systems)- Platinum Sponsor |
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| 11:00 | Refreshments and Networking | ||
| Multi-Track Session (AM) | |||
| CPU User Presentations | |||
| 11:30 | Accelerate your adoption of RISC-V with CORE-V-VERIF Mike Thompson(OpenHW Group) |
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| 11:50 | Accelerating RISC-V testbench development with open source RISC-V RTL and emulation Varun Koyyalagunta(Tenstorrent) |
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| 12:10 | Memory Patterns – Reusable Stimulus for RISC V Memory Subsystem Verification Vibarajan Viswanathan(Condor Computing) |
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| Track 2 - Training Session 1 | |||
| 11:30 |
Doug Smith(Doulos) Gold Sponsor |
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| Track 3 - UVM for AMS Verification | |||
| 11:30 | Mixed-Signal Randomisation - Stimulus and Checkers Peter Grove , Steven Holloway (Renesas) |
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| 12:30 | Lunch and Networking | ||
| 13:30 |
Adnan Hamid (Breker Verification Systems) Gold Sponsor |
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| 14:00 | Practical applications of machine learning in design verification and ISO 26262 practices Dilip Kumar (TessolveDTS Inc) |
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| 14:20 | A Holistic Approach to RISC-V Processor Verification Larry Lapides(Synopsys) Gold Sponsor |
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| 14:40 | Pushing forward the frontiers of formal in Arm CPUs Vikram Khosa(Arm) |
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| 15:00 | Refreshments and Networking | ||
| Multi-Track Session (PM) | |||
| Track 1 - Latest topics in Verification | |||
| 15:30 | Using Symbolic Execution to analyze Hardware TCP/IP Stacks Based on HLS Development Nianhang Hu(University of Nebraska - Lincoln) |
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| 15:50 | Hardware Fuzzing to Secure Modern Hardware Rahul Kande(Texas A&M University) |
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| 16:10 | Verification education: Opportunities and Challenges Ishaq Unwala (University of Houston Clear Lake) |
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| Track 2 - Training Session 2 | |||
| 15:30 | Practical Hacks for SystemVerilog Coverage Doug Smith(Doulos) Gold Sponsor |
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| Track 3 - VHDL Verification | |||
| 15:30 | A pragmatic approach to improving your FPGA VHDL verification Espen Tallaksen(EmLogic) |
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| 16:30 | Event Closes |
Sponsors
VF2024 was made possible through the generosity of the following sponsors. If you would like to become a VF2024 sponsor please Contact Us.
