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Challenges in Verification for Automotive Applications

Conference: Verification Futures 2024 (click here to see full programme)
Speaker: Vijay Kanumuri
Presentation Title: Challenges in Verification for Automotive Applications

Design verification targeted for Automotive SoCs provides several challenges spanning technical, compute, safety, reliability, advanced technologies and complexity of modern vehicles. We will discuss these aspects as part of presentation.

Speaker Bio:

Vijay has a rich 16 years of experience in leading Design Verification teams across SOC Design Verification, Platform IP Design Verification, HSIO/Networking/Infrastructure IPs domains. In various capacity as Design Verification lead, he has led verification across many breakthrough products and platform definition in Automotive and Industrial space. He joined Texas Instruments after his graduation in master’s in computer engineering from UT Austin. In his role starting in IP development and leading SOC DV, he has been instrumental in developing a platform methodology for verification across multiple product lines as well as leading end-to-end SOC DV execution for successful 16nm Automotive ADAS SOCs including post-silicon Test development. He led vendor Technical Review Meetings, evaluating, onboarding new tools, and driving architecture, test plan reviews and execution for first pass silicon success. In his previous role as Design Manager responsible for HSIO/Networking/Infrastructure IPs, he was leading the architecture for low-cost platform and networking IPs, IP procurement and Management Review meetings with external vendors to drive roadmap decision and alignment.

Key Points:
  • Safety and Security targeted Verification
  • Low power
  • Performance and Latency Usecases
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