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Accelerate your adoption of RISC-V with CORE-V-VERIF

Conference: Verification Futures 2024 (click here to see full programme)
Speaker: Mike Thompson
Presentation Title: Accelerate your adoption of RISC-V with CORE-V-VERIF

CORE-V-VERIF is an open-source project supported by the OpenHW Group. Its goal is to provide an open-source environment and work-flow that can be deployed onto any RISC-V processor core. Since December of 2020, OpenHW Group members have successfully used CORE-V-VERIF for end-to-end verification of more than six RISC-V cores.

Speaker Bio:

Mike is a functional verification engineer and manager who has been involved in all aspects of the discipline: simulation, emulation, prototyping and formal verification. He is strong proponent of coverage driven processes in the pursuit of first-time-right silicon.

Key Points:
  • CORE-V-VERIF is an open-source SV/UVM environment for RISC-V cores.
  • OpenHW applies industry leading tools and methodologies to fully verify its open-source RTL IP.
  • CORE-V-VERIF can be used as-is, or by using select components such an Instruction Stream Generator, UVM Bus Agents, Assertion Libraries and Functional Coverage.
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