|Conference:||Verification Futures 2023 (click here to see full programme)|
|Presentation Title:||Verification by Documentation|
With all the innovations in tools to help with functional closure, one that is not fully appreciated is the need for disciplined documentation at every stage of verification. Documentation often is a victim of tight schedules and yet lack of it remains the root cause of schedule slips, many escapes, delays and churn in projects. We will explore different kinds of documents and shine light on this problem. We claim, without due appreciation of this, we can not close the verification gap.
Hemendra Talesara is a distinguished leader in the semiconductor sector in the USA, amassing a rich legacy of over 35 years. He served in senior management roles with IBM, AMD, Synopsys, and many other organizations. Specializing in CPU, GPU, ASIC, and SOC chip design, he boasts profound chip design verification technology expertise. Hemendra's exceptional competencies encompass global team formation, project risk management, and certified corporate governance as a NACD Certified Corporate Board Director. His interests include business Implications of digital disruption, AI, and cyber security. Hemendra's academic journey encompasses an MS in Electrical and Computer Engineering from the University of Texas at Austin and a BE in Electronics and Telecommunication Engineering from IIEST, Shibpur, India. Beyond his professional journey, Hemendra's active involvement in industry conferences, technical journals, teaching, travel, and diverse hobbies showcases his multifaceted persona. With a career defined by inclusive and collaborative leadership, technical prowess, and a commitment to innovation, Hemendra Talesara brings considerable depth to any organization.