|Conference:||Verification Futures 2023 (click here to see full programme)|
|Presentation Title:||Safety and Security challenges in hardware IP development|
Ensuring the trustworthiness in computing is increasingly becoming a challenge in the inter-connected world relying on electronic systems. Security and safety provide assurance that these systems are resilient to malicious attacks and malfunctioning components, respectively. Given the diverse and rapidly evolving market demands, the requirements for both new features and performance significantly increases the probability of security- and safety-related design flaws to remain undetected. This talk will describe the challenges during IP development in efficient identification of relevant risks, and their effective mitigation for safe and secure computing.
Vivek Vedula leads the SDL methodology architecture and development for hardware IPs at Arm. Prior to this, he held several roles at Intel, NXP and Oracle Labs spanning the areas of formal verification, post-silicon validation and HW-SW co-verification. Vivek holds a PhD degree in Electrical and Computer Engineering from the University of Texas at Austin.